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Papilio One/Pro how fast can I flip an output pin?

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Hello,

 

I'm not familiar with FPGA development, so please bear with me if this isn't the right question to ask.

 

Background:

I'm trying to build a system to output PNCode that is pregenerated (to best suit task). In essense I need a whopping big shift register (the max code we use now is 128Kb long) that I can clock accurately and shift out at a predetermined rate.

 

My question is, what's the fastest rate I can achieve using a Papilio? I'd like to flip the output pin at something close to 50MHz ( or as fast as possible really). I understand that the XTAL is 32MHz, and that I can use the internal clock managers to generate higher rate clocks, but how fast can I drive it, and how fast can I realistically drive a GPIO pin?

 

Thanks, and my appologies if this is a stupid question.

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fastest rate is about 1Gbit/s using dedicated serializers, but it's hard to code. You won't want to have this unless using differential outputs, because the signal will be very distorted if you use single ended.

 

What is your application ? For up to 100MHz, you can use a ODDR flip-flop inside the FPGA, and it will work very well.

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I need output a binary bit stream at a specified rate. I need to drive TTL levels into a 50ohm system, but I figured any output conditioning can be accomplished externally.

 

In essence, I have a string of bits (say 1Kb long) and I need to clock them out at a configurable rate (say anywhere from 5MHz up to the max achievable by the output pin). Would this be achievable? And any guesses/estimations as to what the realisitc max is, given internal clock limitations and the number of cycles required to move the data to the pin?

 

Thanks a lot!

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I don't think speed is the problem here, up to 100MHz you should be quite fine.

 

The problem is configuring the rate. Is this supposed to be changed in run-time, or hardcoded ?

 

Realistically speaking, I think you can get up to 500MHz easily, but again, it's hard to code (it will require parallel-serial conversion using OSERDES2). Is your string of bits constant ? If so, it can be accomplished using a Block RAM properly designed for the job.

 

Take a look at this application note from Xilinx: http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf

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I think the rate would be variable, set at runtime. Would it be possible to lock the clock (or the output) to an external trigger? I need to clock the system against a drifted sine wave (for a doppler radar system).

 

The string of bits would also be variable, loaded into RAM during a setup phase. My initial idea was to set up an I/O line that I'd pull low, then feed in the bit stream (loading into ram). Then when ready, I'd pull low a line to start the output stream.

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I'm pretty sure you could just make a one-bit wide BRAM-based FIFO, Clock in your bits on one side, clock the bits out the other side when you need them.

 

It would be a one-shot setup like that. However I am sure you could put some feedback in to allow the same bits to recirculate back into the FIFO.

 

I would have to check, but at least on the Spartan 6 platform each BRAM block can be configured as a 16k x 1-bit, and with using only 8 of the 32 available on an LX9 you have the 128kbits you need.

 

The other way would be just to use them as simple dual port RAM - use a counter on the write port allows you to set the bit values with just three signals "clk", "data_in", "reset". For bonus points you could give it a RS232 interface allowing it to be PC controlled.

 

On the read-out side you will just need an external clk, trigger and data_out. Also have a counter that is held at "all ones" till trigger is asserted, then it plays back the contents of RAM. 

 

Does that sound like what you are after? If so, please feel free to email me off-list if you want a hand implementing it.

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I run regularly at 165 MHz clock speed on the Papilio pro (but not using IOs at that rate), with a little pipelining it'll probably go far beyond 200 MHz for such a simple application.

Output slew rate and drive strength need to be configured in the .ucf file.

 

BTW I might have some code lying around to program an on-FPGA RAM via the USB port (you'd use dual port RAM, one port for programming, one port for output).

But for a start use an inferred RAM (search for that keyword, and / or use the template in Xilinx ISE / PlanAhead) and define your data as initial content.

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