Nadav

Analog IOs for Papilio one

2 posts in this topic

Hi Guys,

I am new to the FPGA world. I am planning to get the Papilio ONE board with LogicStart MegaWing for FPGA and Verilog learning.

My question is about the ADC chip on this wing.

I understand that SPARTAN FPGA family doesn't come with analog IOs, so an external ADC was used, controlled by SPI protocol.

Now lets say I want to play with this option,I guess that I need some kind of Verilog code in order to implement the SPI protocol into the FPGA, am I right?

Is there an exsisting block I can use?

 

I have looked for information about it, but all I found is stuff related to the ZAP IDE, while I want to use papilio as an FPGA development platform.

 

Thanks:)

 

Nadav

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