offroad

Yet Another VGA generator

11 posts in this topic

Sometimes we all wish for "only one more LED". Now how about 307200 LEDs, all RGB, perfectly arranged in a square? (And I bet also your monitor has an unused analog input...)

Seriously, an RGB monitor can be a useful debugging tool, a poor man's logic analyzer.

 

The hardest step is probably the first, and that is to get some picture at all.

That's why I'm posting this VGA timing generator. It's rather compact (less than 200 lines, many of them comments), but it takes no shortcuts with the sync generation.

post-36723-0-27187300-1395089107_thumb.j.

 

The use of an inferred DSP48 for the test picture (via "*") is heavy-handed - but hey, we already paid for it, so let's use it.

This is the planAhead project:

RGB.pa.zip

 

The interesting file is RGB.srcs/sources_1/imports/src/top.v

Further, there is a generated 32-to-25.175M PLL (approximate frequency) and the constraints file.

The latter is for a Xess RGB wing in Papilio Pro port "C".  Pins may need to be re-mapped, depending on connections.

 

Now, how to use it for more than a test picture:

The generator provides X and Y as numbers, "blank" (here RGB must be zero), besides HSYNC and VSYNC signals to the monitor.

A typical implementation would need some processing delay on X and Y, simply delay HSYNC and VSYNC by the same amount.



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Hey, very cool offroad. Another tool for our bag of tricks. :)

 

I'll schedule this for a post to the blog.

 

Jack.

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Hmm interesting idea.

 

You gave me another idea though. Since you mention LEDs, I have a couple of 32x32 RGB panels that suddenly reminded me of a old application I wrote when I was a sysadmin at my University. Basically, we had a problem back then (it was in 94 if I recall well). Most of the networking infrastructure was 10-base2, and we still had parts in 10-Base5, and some computer servers were actually in teachers/investigator offices. We hated when we were the last ones to know when a networking problem had occurred, so I developed a small application for my GNUStep environment, and it could display up to 40 host status in a small area, using small leds to depict their status. It also could fire up a siren warning.

 

wmnetmon.gif

 

Would be perhaps interesting to use a real RGB panel for this :)

 

Another idea is to map the RGB inside the FPGA like they'd have discrete wires...

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I have many years experience programming in C and doing electronics and simply want an example that I can load and run in the ISE and this looked great but has no .xise file which seems to be needed to load a project. It would be so nice to actuually have some projects to load without problems for my Papilio Pro. I have found that looking at code is a very good way to start but debugging code is not. I just feel sure there must be something that everybody didn't mention because its too obvious. Given the idea is meant to be that this is as well supportede as the Arduino, I think it might be worth while actually checking and perhaps re-writing the Quick Start pages so that they don't assume a bunch of steps. The writing should preferable be done by someone like me who is new to the Papilio and not well seasoned in Linux. Anyway overall I am having fun but I would love to just be able to download this RGB project load it into the ISE and use it. :-)

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>> and simply want an example that I can load and run in the ISE

Hi,

 

I know what you mean... it was meant to be just that.

Fortunately, the answer is simple: It uses "planAhead", not "ISE". It is a (largely) independent alternative to ISE that got installed at the same time.

On Linux, it should start with "planahead" or "planAhead", after setting the environment variables.

 

Once you build it successfully (you may have to click "generate bit file" after synthesis and implementation), you get the .bit file. Upload that with Papilio loader and you should be able to see the signals on an oscilloscope.

 

------

 

there are largely two "tracks" how to use the Papilio: As a "softcore" Arduino, and at RTL level. This example is the latter: You won't find any processor, "C" or sketches, it's all done in reconfigurable hardware coded in Verilog.

 

---------

 

There is no need for a wing. I usually connect HSYNC, VSYNC, GREEN, GROUND (sometimes RED, BLUE) with Dupont male-female wires straight to the sub-D cable. It violates the electrical specs, but hey, monitors are cheap.

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Thanks OffRoad for your time and reply. Yes I am keen to follow RTL and have no intention of using Papilio as an Arduino. However I had assumed that the use of the name implied an easy startup process but it took half an hour to get the Arduino development environment running and two days for the Papilio substantually due to poor documentation.

 

Your code is working with the VGA Wing (with a few pin changes) on my system, I can see it on my oscilloscope, but I don't have a 640x480 monitor! For other readers I have explained the process I went through below.

I found references to 640 and 480 in the code and also variables for the porches sync pulses etc but could not see where to adjust the clock.

 

(1) Is it easy to adjust the clock? i.e. to run 1280x1024 for example.

 

Bare in mind I have never used any HDL before in my life so I would be unlikely to spot it myself. Yes I know I should read through some tutorials, and I intend to but there is nothing like hacking as a way to learn.

 

(2) I like the Plan Ahead environment, is it the way things are going? Can I focus on it in confidence as the choice for the future or should I still be considering the ISE? I read about PlanAhead v. ISE from http://www.xilinx.com/tools/planahead.htm but it didn't really give an answer or are they simply to parallel approaches as you previously suggested?

 

I'll tell you one thing. I enforced a rule about curly brackets in C/C++ in my company that any opening bracket must be on the same line or in the same column as its corresponding closing bracket. This creates a highly structured appearence in the code. The alternative is a collection of rules to deal with various statements in often subtle ways which when there are many levels of nesting over large blocks of code ends up, well, "ellaborate", shall we say. In Varilog of course there is "begin" and "end" so I was hoping the curly braces argument would disappear. But no, sadly for me when I looked at your code I see it hasen't! ;-) Eeek I think I will run to VHDL and hide ;-) Anyway please don't feel any need to give a serious reply to this point which is quite off topic.

 

Below, just for the benefit of other readers here is how I got things going for the code as it stood to provide 640x480. Thank you for writing it and sharing it.  Tom

 

I typed   sudo /opt/Xilinx/14.7/ISE_DS/PlanAhead/bin/setupEnv.sh   to set the environment variables
I typed   sudo /opt/Xilinx/14.7/ISE_DS/PlanAhead/bin/planAhead   to start the application

 

On startup I got these "critical warnings" which I ignored.
 [Project 1-19] Could not find the file /home/tom/Computronics/Papilio/Xilinx/RGB/RGB.srcs/sources_1/imports/src/vga1440x900.vhdl.
 [Project 1-19] Could not find the file /home/tom/Computronics/Papilio/Xilinx/RGB/RGB.srcs/sources_1/imports/src/PLL106.v.

 

In RGB/RGB.srcs/constrs_1/imports/src/RGB_papilioPro.ucf I changed the output pins so that the VGA Wing would work. I replaced;

 

NET RGB_B3     LOC="P123" | IOSTANDARD=LVTTL;                                # C8
NET RGB_G3     LOC="P124" | IOSTANDARD=LVTTL;                                # C9
NET RGB_R3    LOC="P126" | IOSTANDARD=LVTTL;                                # C10
NET RGB_B4    LOC="P127" | IOSTANDARD=LVTTL;                                # C11
NET RGB_G4    LOC="P131" | IOSTANDARD=LVTTL;                                # C12
NET RGB_R4    LOC="P132" | IOSTANDARD=LVTTL;                                # C13
NET RGB_HSYNC    LOC="P133" | IOSTANDARD=LVTTL;       # C14
NET RGB_VSYNC    LOC="P134" | IOSTANDARD=LVTTL;       # C15

 

With;

 

#My new pins to work with vga wing
NET RGB_VSYNC     LOC="P123" | IOSTANDARD=LVTTL;                                # C8
NET RGB_HSYNC     LOC="P124" | IOSTANDARD=LVTTL;                                # C9
NET RGB_B3    LOC="P126" | IOSTANDARD=LVTTL;                                # C10
NET RGB_B4    LOC="P127" | IOSTANDARD=LVTTL;                                # C11
NET RGB_G4    LOC="P131" | IOSTANDARD=LVTTL;                                # C12
NET RGB_R4    LOC="P132" | IOSTANDARD=LVTTL;                                # C13
NET RGB_G3    LOC="P133" | IOSTANDARD=LVTTL;       # C14
NET RGB_R3    LOC="P134" | IOSTANDARD=LVTTL;       # C15

 

Then clicking on the "play" icons on the left enabled me to go through the process of running Synthesis, running Implementation and then generating Bitstream. The resulting file top.bit was then avalable to download to the papilio using

 

I typed  /opt/GadgetFactory/papilio-loader/papilio-loader.sh

 

entered the file path which from the RGB folder is  RGB/RGB.runs/imple_1/top.bit

 

and then pressed the run button. All downloaded sucessfully but since this is for 640 * 480 I don't have any monitor that will work at this resolution!
 

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Welcome to FPGA tool hell, where "Half an hour" doesn't even register as "easy". It's nothing, a glitch, a hold time violation :)

 

>>and I intend to but there is nothing like hacking as a way to learn.

agree with that, but try to make it work and then change one thing at a time.

It is a fairly standard resolution and works well with plain wires because of the modest pixel clock.

Nowadays, monitors are "multisync" and adapt automatically. OK, some don't and start to burn. In this case, try another monitor ...

 

I wouldn't mess with the parameters before establishing a working baseline, rather try a couple more monitors. Ideally one that complains "signal not found" or "resolution not supported" when the signal doesn't make sense.

 

>> I like the Plan Ahead environment, is it the way things are going? Can I focus on it in confidence as the choice for the future or should I still be considering the ISE?

I'd use ISE to manage the project nowadays. PlanAhead was the newer version, but development is now officially stopped and it seems half-baked as ISE replacement. There is no point talking about what "should" be. On the bottom line, the tools work - somehow -, cost nothing and are reasonably un-crippled.

 

>> Eeek I think I will run to VHDL and hide

Oh, Verilog is a professional tool, makes no pretense of being pretty, friendly or easy but gets the job done with the smallest number of keystrokes. As for VHDL, actual death by carpal tunnel syndrome is fortunately rare :)

Seriously, don't expect any meaningful discussion of Verilog-vs-VHDL or what is The correct way to format code.

 

Actually, the code should be indented consistently (but not K&R style). Maybe try a different text editor or re-run emacs ESC-x indent-all.

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I think Xilinx is now more focused on Vivado than other tools - but they have to maintain at least the core of it - and that means ISE.

 

Regarding Verilog/VHDL: I have a mixed opinion. I stick with VHDL because it's more like a general-purpose language than Verilog. There are pros and cons for each of them - and formatting code is not one of them actually. Nor is it the number of keystrokes - verbosity is not necessarily a bad thing.

 

VHDL has many interesting stuff which may not be used for synthesis, but is indeed used for simulation. Verilog, in other way, has assertions, which simplify testing.

 

Back to original thread:

 

since this is for 640 * 480 I don't have any monitor that will work at this resolution!

 

You have indeed an odd monitor - care to share which monitor it is ?

 

Alvie

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Hi,

 

what I meant is this:

Last Updated October 2013

 

With the ISE Design Suite 14.7 release back in October of 2013, ISE has moved into the sustaining phase of its product life cycle. In the future, while there are no more planned ISE major releases, Xilinx will continue it's superior technical support and may release periodic updates and patches.  Xilinx recommends signing up for “My Alerts” at http://www.xilinx.com/support/answers/18683.htm to keep you informed.

 

"Superior technical support", means that their data2mem utility only segfaults on bad input but it won't set your computer on fire :)

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Yes Yes Yes. Ok it would not work on three different monitors. I changed the timings for different resolutions but all monitors seemed to either say "out of timing" or just go to sleep. Looked at signal on scope and all timings looked correct. Finally set another machine to 640x480 and looked at signal on scope. Ah seems like I had swapped the vsync and hsync Now ofcourse it all works fine in all resolutions.

 

In above Replace;

 

NET RGB_VSYNC     LOC="P123" | IOSTANDARD=LVTTL;                                # C8
NET RGB_HSYNC     LOC="P124" | IOSTANDARD=LVTTL;                                # C9

 

With;

 

NET RGB_VSYNC     LOC="P124" | IOSTANDARD=LVTTL;                                # C8
NET RGB_HSYNC     LOC="P123" | IOSTANDARD=LVTTL;                                # C9

 

Oh dear :-)

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