Jack Gassett

JTAG Logic Analyzer

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Ok, I went down the rabbit hole and am just now coming up for breath!

 

After an epic week long battle that found me obsessed with this one task I have something pretty cool working on the Papilio.

 

Let me start from the beginning, at the end of last week when I was working on the new board design I realized that there might be a huge problem with trying to connect the channel A UART pins from the FT2232 to FPGA I/O pins. I pulled out the trusty Papilio One and tested it out, sure enough, when the Papilio is being programmed all of the I/O pins go to 3.3V which will interfere with the TCK and TDO pins during jtag programming. So the way I had things wired up was not going to work. I started thinking about solutions, adding an IO switch would solve the problem but I'm not super thrilled about doing so. So I started thinking about why we need it connected and it really comes down to being able to use channel A for communications after the FPGA is programmed. Well, we already have an example of doing that, we use the bscan primitive to program SPI Flash...

 

So I thought, well before I commit to adding an IO switch to the board I should spend a couple days connecting the Sump Logic Analyzer to the bscan primitive so we can use the FT2232 channel A or logic analyzer debugging and use channel B for normal uart communications to our Soft Processor. It's going to be hard to do but I should be able to bang it out in a couple days... Famous last thoughts...

 

Every day I made just enough progress to keep me completely obsessed for the next day, just a little bit more and it will be working... Well it dragged on way longer then I expected but I have a first working prototype! There are still some bugs to squash but it is working well enough to prove that we can use channel A for debugging and there is no need to add an IO switch to the new board.

 

Here are some details:

 

This is what the schematic looks like: (I'll be moving the bscan_spi symbol into the Logic Analyzer symbol so you just drag and drop the LA symbol)

post-29509-0-24605900-1390602871_thumb.p

 

Here is Channel B being used for regular communications while Channel A is being used to debug the Wing_AL0 pins with the Logic Analyzer, they both work perfectly at the same time:

post-29509-0-20328600-1390602959_thumb.p

 

The way this works is that I modified the papilio-prog application to add a jtag passthrough mode, it creates a network socket and will pass communications through to the FPGA:

post-29509-0-72453500-1390603024_thumb.p

 

Finally, you use the Logic Analyzer client to connect to the Network socket:

post-29509-0-43485400-1390603056_thumb.p

 

It's going to be a great thing to have in our bag of tricks! Like I said, there are still some wrinkles to iron out, but I should have a release out soon!

 

Jack.

 

 

 

 

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I posted the query below in the "Open Bench Logic Sniffer with 64MB capture buffer" thread, but perhaps this is a better choice.

 

In the post below, the "server" being referred to is the socket to JTAG over USB/FTDI 'server'; or what Jack is referring to above as "The way this works is that I modified the papilio-prog application to add a jtag passthrough mode, it creates a network socket and will pass communications through to the FPGA:". Perhaps a peek at that code would answer my points 1 and 2 below. I didn't see this passthrough mode in the GitHub files for papilio-prog, but I could have just missed it.

 

From what I gather, it appears that all this may be part of the ZPUino files / library, so I may spend some more time looking there.

 

However, I'm mostly looking for the bare bones HDL and 'C' rather than utilizing schematic entry so as to more easily integrate with my current project.

 

Jack Gassett, on 06 Feb 2014 - 6:02 PM, said:snapback.png

I might use your server code, mine is pretty ugly...

Hi, Jack;

 

I wonder if you might share 1) source for your server, 2) perhaps configuration details / examples for the FT2232D, and 3) HDL for the fpga I/O to make this all work. I'm very curious about exactly how this communications path works. A forum link, or links, would be fine if you've already documented it.

 

Thanks in advance.

 

dandreat

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Ah. I think I've found most of what I'm looking for.

 

* The HDL sources are in the hierarchy of the GadgetFactory GitHub Papilio-Schematic-Library/examples/ repository.

 

* And, I've discovered the Windows executable for the server in the GadgetFactory GitHub Papilio-Schematic-Library/examples/Virtual_Dashboard/papilio-prog-jtag-server/ repository.

 

BUT, I can't seem to find the source for the papilio-prog-jtag-server. I think I could understand how this works end-to-end if I could take a look at that. Any tips for where I might find that source would be appreciated.

 

Thanks in advance!

 

dandreat
 

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