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ADAU1761 Audio codec.

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Hi, a question mainly for Jack, but others might be able to help me.

 

So I'm half way through the design of the board, using a SSOP28 package. I'm going to have an onboard linear regulator for the 3V3 for the analog side of the codec, given that the Papilio Pro uses switching regulator for its own 3V3 supply - so that is an easy decission. However, how much current is spare on the Papilio One / Papilio Pro's 3V3 line for the digital side? Should I have a second regulator for the digital side of that includes the 12.288MHz crystal?

 

Also, I'm going to use a 12.288MHz crystal, giving only a 48kHz output rate. Any comments about that? The other option is to make it a 16 bit wing, and use just one extra pin to supply a master clock sourced from the FPGA - however it will most likely have higher jitter.

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Hi, a question mainly for Jack, but others might be able to help me.

 

So I'm half way through the design of the board, using a SSOP28 package. I'm going to have an onboard linear regulator for the 3V3 for the analog side of the codec, given that the Papilio Pro uses switching regulator for its own 3V3 supply - so that is an easy decission. However, how much current is spare on the Papilio One / Papilio Pro's 3V3 line for the digital side? Should I have a second regulator for the digital side of that includes the 12.288MHz crystal?

 

Also, I'm going to use a 12.288MHz crystal, giving only a 48kHz output rate. Any comments about that? The other option is to make it a 16 bit wing, and use just one extra pin to supply a master clock sourced from the FPGA - however it will most likely have higher jitter.

 

If we are connected to USB then the maximum current available for all voltage rails is 500mA. looking at the datasheet for the switching regulator used with the Pro it says that max current per rail is 600mA. So if you don't power through the USB port and use the Vin pins instead then we can source 600mA for each voltage rail.

 

So depending on what design you are running on the FPGA there should be lots of current available. You can run the Xilinx power estimator on any project to see what kind of power it uses. I think I remember running it on the ZPUino at one point and it was using something like 80mA on 1.2V and 150mA on 3.3V... Don't quote me on that, its what I vaguely remember. It was when I was trying to decide if 600mA was going to be enough current, I remember thinking that there was LOTS of headroom left.

 

Jack.

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If we are connected to USB then the maximum current available for all voltage rails is 500mA. looking at the datasheet for the switching regulator used with the Pro it says that max current per rail is 600mA. So if you don't power through the USB port and use the Vin pins instead then we can source 600mA for each voltage rail.

 

So depending on what design you are running on the FPGA there should be lots of current available. You can run the Xilinx power estimator on any project to see what kind of power it uses. I think I remember running it on the ZPUino at one point and it was using something like 80mA on 1.2V and 150mA on 3.3V... Don't quote me on that, its what I vaguely remember. It was when I was trying to decide if 600mA was going to be enough current, I remember thinking that there was LOTS of headroom left.

 

Jack.

The efficiency of the switching regulator is quite high (~90%) so if you draw 600 mA on the 3.3V rail it will only draw 600 * (3.3/5) / 0.9 = 440 mA from 5V USB.  This would leave 60 mA from the USB port for 1.2V which translates to 225 mA on the 1.2V rail.  So I think it's pretty safe to say that you can use the full 600 mA on the 3.3V rail even if you are powered from the USB port.

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