Jack Gassett

The next generation Papilio - help me shape it.

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sorry to spoil the fun but I would leave away the image. On a T-shirt for a little girl, yes. On an electronics component, no. My $0.02 :)

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BTW the thin metal areas at the top and left edge of the "bottom" board may turn into resonators at ~500..2000MHz.

Don't know how much this matters, a two-layer board will be quite nasty to start with. Ground... what ground...

Anyway, they seem to serve no functional purpose. On my own board I'd remove them.

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the thin metal areas at the top and left edge of the "bottom" board may turn into resonators at ~500..2000MHz.

 

 

There are two kinds of EEs: Those who design antennas on purpose, and those who build antennas accidentally :-)

 

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I vote red with white soldemask. the picture logo is fine not just for little girls :)

The black is nice but as was pointed out there could be issues. then there's the debate about glossy black vs matte black.

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ok compromise then, a smaller butterfly :)

It's a good looking board but the curved graphics on top of the straight traces will take some time to get used to.

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BTW the thin metal areas at the top and left edge of the "bottom" board may turn into resonators at ~500..2000MHz.

Don't know how much this matters, a two-layer board will be quite nasty to start with. Ground... what ground...

Anyway, they seem to serve no functional purpose. On my own board I'd remove them.

 

Those are the 5V power lines so there should be no signal on those lines. The only signals on the bottom side of the board are the AVR signals which are never going to be above 16Mhz. This is also a 4-layer board with a fully unbroken ground plane... All the high speed signals are on the top side of the board with the ground plane directly underneath.

 

Jack.

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Ok, as for the question of the color scheme... I was really leaning towards matte black soldermask with red silkscreen. But you all bring up some very valid points, I read up on why the teensy changed colors and I don't want to deal with the same type of issues. So for production I think red soldermask with black silkscreen will be the target.

 

However, I really think the matte black soldermask and red silkscreen POPS. I think it is worth dealing with the yield problems for a Kickstarter campaign. So I think I will have an exclusive limited run of that color scheme for the Kickstarter. It will bring attention to the board and more importantly the software that is being made along with this board. It also gives Kickstarter backers an exclusive perk...

 

Jack.

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Those are the 5V power lines so there should be no signal on those lines

 

Power lines and ground lines are where all current flows to and fro. So yes, all signals are present there.

 

I therefore assume you were meaning something else :)

 

There's nothing as noisy as power line. Ground is no exception, "the spice must flow".

 

Alvie

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Hi,

 

I wasn't referring to the traces as such, but the free-standing metal at the edge of the board.

The long one on top is the worst offender, then the one on the left side.

Those are likely to pick up interference and couple it into the circuit.

 

For example, a GSM cell phone blasts out around 1 W for no other reason than to say "hello" to the basestation.

Even if only 1 % of that gets coupled, it's still a lot of power for an interfering signal. Yes, it'll probably work well enough as it is, but common sense tells to remove them, or ground with more vias.

 

This isn't a high performance design, might still be of interest:

Large grounds that are cut by traces, without plenty of vias, can also be problematic. The combination of inductance (from long paths across the ground plane) capacitance (from ground vs next layer) and low losses (all copper and FR4) can play some strange tricks. Don't know how much a via costs to drill, but generally you go by "better safe than sorry", also because it's difficult to debug.

 

post-36723-0-22558300-1393027692_thumb.p

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He is just giving out unique numbers, not VID/PID numbers.  For that you will probably have to purchase a VID number from the USB consortium which will set you back a few bucks (like $5000).

 

From his web site:

Is that legal ?

Absolutly.

We are talking about numbers. Nothing else.

This website is only a annuary of useful numbers.

We have no association or contract with anyone.

 

 

Here is info about how to get a VID from the USB.org web site:

http://www.usb.org/developers/vendor/

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He is just giving out unique numbers, not VID/PID numbers.  For that you will probably have to purchase a VID number from the USB consortium which will set you back a few bucks (like $5000).

 

Or for $4000 you can become a member for a year and get a "free" VID...

 

"We have no association or contract with anyone."

 

Of course, absolutely *no* association with anyone.  Nope, no way those numbers could be used as VID/PID combinations.  Not. Ever.

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Perhaps FSF/OSHW or other similar entity can buy a VID from them, and re-sell PID to open designs. For a 5K Vendor ID, since there are 65536 PID (some probably reserved), that would be less than ten cents.

 

If they would delegate each of them at, let's say, $5 (one time payment) each PID, then we could inject some money into the "open source" system, and make everyone happy.

 

I have no contacts in OSHW. Does any one have ? I am not very fond of them, but this would benefit everyone IMHO.

 

Alvie

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Perhaps you're not familiar with the (I thought) well known post by Arachnid labs, which was covered by Hack-a-Day and The Register as well as Slashdot and others. While what you propose is perfectly sane, resale of PIDs is specifically forbidden by the USB-IF rules.

 

At the end of the day, despite Magnus' comment about a lawsuit earlier, I think you can just do what everybody else does. Completely ignore the USB-IF and allocate your own VID/PID to yourself or reuse one for a similar product. The USB-IF has no legal recourse to prevent you from using a number , as long as you don't advertise your product as USB compliant. It's the only way to deal with money hungry dicks like them who refuse to support the FOSS community.

 

Perhaps don't even mention the board has USB connectors and call them High Speed Serial Interconnects.

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Alex, "Completely ignore the USB-IF and allocate your own VID/PID to yourself or reuse one for a similar product."

 

There are practical reason not to do that -- I'm sure you know this, but the host computer identifies which driver to load via that VID/PID.  If you sell a product with a vid/pid which collides with an existing product, it can lead to unhappy users unless your hardware is a (nearly) exact functional replacement for the board whose ID you are squatting on.

 

The right technical solution would have been to have a 128b ID space and then there wouldn't be the need to be so miserly with allocation of this resource.  Too late now, though.

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Heh thanks Jim, I was being far too subtle maybe. By "similar product" I mean just give it the same VID/PID as an Arduino Leonardo. While this does not seem "proper" since the Arduino guys paid real money to USB-IF and they don't want others tagging along on it plus the USB-IF does not allow this, in practice, the chip as configured is a Arduino Leonardo for all intents and purposes so it deserves to reuse the already allocated VID/PID

 

From a business/legal point of view, what Jack could do is, after of course running the factory tests on all the components, blank out the Arduino firmware prior to selling it. What firmware people choose to put on it afterwards is outside his control, if you catch my drift.

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Hi,

 

I wasn't referring to the traces as such, but the free-standing metal at the edge of the board.

The long one on top is the worst offender, then the one on the left side.

Those are likely to pick up interference and couple it into the circuit.

 

For example, a GSM cell phone blasts out around 1 W for no other reason than to say "hello" to the basestation.

Even if only 1 % of that gets coupled, it's still a lot of power for an interfering signal. Yes, it'll probably work well enough as it is, but common sense tells to remove them, or ground with more vias.

 

This isn't a high performance design, might still be of interest:

Large grounds that are cut by traces, without plenty of vias, can also be problematic. The combination of inductance (from long paths across the ground plane) capacitance (from ground vs next layer) and low losses (all copper and FR4) can play some strange tricks. Don't know how much a via costs to drill, but generally you go by "better safe than sorry", also because it's difficult to debug.

 

attachicon.gifa.png

 

Ok, thank you for pointing those out, indeed better to be safe then sorry. I just cleaned them up.

post-29509-0-72332200-1393211917_thumb.p

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I agree, black is too dominant.

I like the red as well.

 

Hey Jack,

the name Papilio DUO sounds good. I resembles the Arduino DUE naming concept (different meaning though between DUE and DUO), where you make a major upgrade step.

Secondly, you point to the fact that there are 2 processing chips: FPGA and ATmega.

 

some remarks on the PCB layout:

- the ground traces on the LTC3419 are too weak (TOP layer) - pin 5 & 6. Make a small GND polygon around those pins (and cap C3), directly connected to GND layer with via.

- same for the main power pin of the LTC3419 - make trace as thick as possible up to pin 7.

- all 5V power traces on entire PCB should be wider

- some atmega ADC pins are shared with digital pins; this might cause ADC noise issues.

- I wonder if the FPGA has enough decoupling caps. The datasheet recommends 17.

      VCC-int and VCC-aux is ok.

      VCC0_1 VCC0_3 is ok (both banks have each 2 caps)

      VCC0_0 VCC0_2 only have 1 cap each. I would add a cap on pin 63 and one on pin 122

- at the top right connector, you have (from top to bottom) 2x 3V3 and 2x GND. The GND might conflict with shields as this is the place for the +V.

   Would it make sense to switch around the 3V3 & GND?

- can you add IOREF pin on connector (next to RST pin)  (you would need to move R31).

      IOREF is an important reference for shields. Connect 3V3 to this.

- some traces on layer "Route 3" can be more "fluent" and straight

 

For the rest, VERY NICE DESIGN !!

 

Dan,

Thank you for taking the time to look at the design and point out these problems. A couple of them were very serious problems that I completely missed!! You saved my bacon on a couple things here...

 

I took action on almost all of the things you pointed out and have modified the design accordingly. I didn't add any more decoupling caps though, and there is not much I can do about the shared ADC pins, we need those for JTAG debugging...

 

 

- at the top right connector, you have (from top to bottom) 2x 3V3 and 2x GND. The GND might conflict with shields as this is the place for the +V.

   Would it make sense to switch around the 3V3 & GND?

 

It was setup this way to support PMOD's... Since this was based on a pre-existing design I thought I had personally added the 5V pins at top and it was safe to change them. I didn't look at the actual Mega footprint... That would have been a serious problem. I changed it back to 5V like on the Mega footprint which means that we can only connect a PMOD to the bottom portion of the header...

 

Anyway, I think that should finish up the design unless anyone else points out any more problems...

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