The next generation Papilio - help me shape it.


Jack Gassett

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The problem with a lot of the so called "free" PCB design programs out there is that they are offered by a specific PCB plant vendor but once you designed your PCB you have to submit the design for manufacture with that vendor. I find this lock in unacceptable.

 

If you're super poor go for Kicad or Eagle Free

If you have money pay for Eagle Pro

If you're doing this for a living, your employer has probably already inflicted Altium upon you so the point it moot.

 

Anything else you're probably just asking to do things the hard way.

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The problem with a lot of the so called "free" PCB design programs out there is that they are offered by a specific PCB plant vendor but once you designed your PCB you have to submit the design for manufacture with that vendor. I find this lock in unacceptable.

 

Unless something has changed, of the ones I mentioned, only ExpressPCB is locked in to a PCB vendor.  (Or is Designspark locked in as well?)  They're sort of like the Front Panel Express of PCBs, and that's not necessarily a negative...   :)

 

If you're super poor go for Kicad or Eagle Free

If you have money pay for Eagle Pro

If you're doing this for a living, your employer has probably already inflicted Altium upon you so the point it moot.

 

Anything else you're probably just asking to do things the hard way.

 

LOL about Altium, we do indeed have that at the day job!

 

I know people who are happy with Diptrace and Rimu, and they are both cheaper than EAGLE Pro...

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Hi all,

 

Ok now it works with my Eagle v6.4

If I download the files .brd & .sch 'as-is', they don't work - the content is rubbish.

I need to view the files in 'raw', copy/paste to text editor, and save corrrespondingly to .brd or .sch.

I never had to do it this way before, so I don't understand what I'm doing wrong.

Anyway, I can read the files now.

 

thanks,

-Dan

 

PS: I don't think there is a discussion about Eagle or not for the Papilio, for me Eagle is a de-facto given.

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Ok, I'm very close to pulling the trigger on the first batch of prototype PCB's for this design... Before that happens though I could use some advice on what to call it. I'm leaning towards Papilio DUO right now but am open to other names.

 

I've thought about Papilio Lab, Papilio eLab, Papilio Duet...

 

What do you guys think? Something even better?

 

Jack.

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Ok, the problem was with the tool I was using to view the gerbers not the imports I was doing...

 

So looking at 3D exports of the boards shows some problems that need to be cleaned up, but I'm trying to figure out a nice color scheme here. I really like how clean black PCB's look so trying these out first.

 

Here is black with red silkscreen:

post-29509-0-77255200-1392945292_thumb.p

post-29509-0-66477500-1392945290_thumb.p

 

Here black PCB with Arduino color silkscreen:

post-29509-0-49239100-1392945288_thumb.p

post-29509-0-78350000-1392945285_thumb.p

 

Thoughts?

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Ok, the problem was with the tool I was using to view the gerbers not the imports I was doing...

 

So looking at 3D exports of the boards shows some problems that need to be cleaned up, but I'm trying to figure out a nice color scheme here. I really like how clean black PCB's look so trying these out first.

 

Here is black with red silkscreen:

 

Have you seen this?

http://dangerousprototypes.com/forum/viewtopic.php?f=68&t=5755

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I agree, black is too dominant.

I like the red as well.

 

Hey Jack,

the name Papilio DUO sounds good. I resembles the Arduino DUE naming concept (different meaning though between DUE and DUO), where you make a major upgrade step.

Secondly, you point to the fact that there are 2 processing chips: FPGA and ATmega.

 

some remarks on the PCB layout:

- the ground traces on the LTC3419 are too weak (TOP layer) - pin 5 & 6. Make a small GND polygon around those pins (and cap C3), directly connected to GND layer with via.

- same for the main power pin of the LTC3419 - make trace as thick as possible up to pin 7.

- all 5V power traces on entire PCB should be wider

- some atmega ADC pins are shared with digital pins; this might cause ADC noise issues.

- I wonder if the FPGA has enough decoupling caps. The datasheet recommends 17.

      VCC-int and VCC-aux is ok.

      VCC0_1 VCC0_3 is ok (both banks have each 2 caps)

      VCC0_0 VCC0_2 only have 1 cap each. I would add a cap on pin 63 and one on pin 122

- at the top right connector, you have (from top to bottom) 2x 3V3 and 2x GND. The GND might conflict with shields as this is the place for the +V.

   Would it make sense to switch around the 3V3 & GND?

- can you add IOREF pin on connector (next to RST pin)  (you would need to move R31).

      IOREF is an important reference for shields. Connect 3V3 to this.

- some traces on layer "Route 3" can be more "fluent" and straight

 

For the rest, VERY NICE DESIGN !!

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What tool are you using to create those pictures?  Do I see SketchUp axes there?

 

FWIW, I like the red solder mask with the white graphics, and it does match the other boards you've done...

 

Using EagleUp to export from Eagle to Sketchup.

http://www.gadgetfactory.net/2011/11/news-eagleup-for-viewing-hardware-designs-in-google-sketchup/

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