Jack Gassett

The next generation Papilio - help me shape it.

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Magnus you're such a tease. That is a marvel of miniaturization. You must tell us more about it. BTW where do you get your boards done? What are the specs for the 4 layer ones, trace/space min widths, min vias etc

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The board is 20 mil thick, 4 layers and has 6 mil via holes and 7 mil traces but the trace spacing requirement is 3 mil due to the 0.5 mm BGA pattern.

The Xilinx recommended PCB design rules has 0.27 mm BGA (L) and via (VL) land diameter and with a diagonal spacing of 0.35 mm (D) the remaining gap is 0.35 - 0.27 = 0.08mm which is a little over 3 mil.  See attached drawing.

 

I have been getting my boards from PCB Universe for quite some time.  You wont get this kind of boards from Seeed or OSH Park...

post-36465-0-38476500-1391785060.png

post-36465-0-42869100-1391785075.png

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You mean, other than just "cute"? No idea :-)

 

You wont get this kind of boards from Seeed or OSH Park...

 

Also, you won't get them under $100/each unless you want at least 5 (you pay $480 for the batch...)

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>> anyone guessing what this is?

anything that involves a hot glue gun has my approval (shoot!)

 

I have a couple of eprom chips lying on my desk with the intended purpose of sticking them to the back of the FPGA one day...

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Moving right along here, I hope to have this design finished by the end of the week.

 

I just finished placing and routing the FT2232H portion of the design. All routed and no DRC errors:

post-29509-0-05730800-1392068434_thumb.p

 

On to the power supply next.

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Jack: did you observe my idea of breaking the JTAG connections so to allow using the FT2232H to be used to program other JTAG devices on the chain ?

 

I think a simple header+jumper would do it, or an unpopulated header plus a user-cuttable PCB connection, allowing to break the JTAG chain.

 

Alvie

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Jack: did you observe my idea of breaking the JTAG connections so to allow using the FT2232H to be used to program other JTAG devices on the chain ?

 

I think a simple header+jumper would do it, or an unpopulated header plus a user-cuttable PCB connection, allowing to break the JTAG chain.

 

Alvie

 

Alvie, Channel B MPSSE is fully connected to the FPGA. So we can make a bit file to connect those JTAG pins any way that we want, no need to do anything fancy with Channel A JTAG pins.

 

Jack.

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I was visiting with Jingfeng over at LinkSprite the other night and we were talking about this board. I mentioned that I wanted to be able to use the FPGA/FT2232H to debug the AVR ATmega32u4 chip and he pointed out that I have the ICSP port connected but in order to debug I need the JTAG port. Doah!

 

Time to think about some reconfiguring of free pins... We need 4 more pins to connect the AVR JTAG port.

 

There are two approaches I could take here:

 

1) I've already re-arranged how the GPIO pins are connected to make routing easier. This is fine because I'm going to adjust the pin configuration in the Arduino IDE to account for these changes... So I could take this even further and shuffle pins around even more. The JTAG pins are dual purpose with the ADC pins and are currently connected to ADC2-5. If routing permits, I could swap out those 4 ADC pins with other ADC pins that are currently being used for GPIO. This would have the effect of connecting those JTAG pins to the FPGA as GPIO. The downside is that if I shuffle pins around too much I might miss something important and realize it later on down the road and highly regret it. With the current re-arranging I just connected the same pins in different order, but the same multi-purpose pins are still connected. What I'm proposing here is to drastically change the Leonardo design, I will have to carefully study the datasheet to try not to miss something important.

 

2) I could use the configuration pins of the FPGA to connect dedicated FPGA pins to the JTAG pins of the AVR. Right now I have HSWAP, M0, and M1 connected directly to ground and 3.3V. I could use pullups/pulldowns during configuration and then use them as GPIO after configuration. It depends on what the AVR would do at power up... TMS, TDO, and TCK should be inputs on the AVR so they should just float... But TDI would need to be connected to a non-configuration pin because it could be driven by the AVR at startup. I already decided to do away with controlling the AVR reset line from the FPGA so that is a free pin we can use.

post-29509-0-78770400-1392226401_thumb.p

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Ok, after looking at the datasheet I don't like option 1 either. I also am seeing that I want to keep the ICSP port connected as well... The ICSP is the only SPI port on the chip, we definitely want that connected...

 

Option 1 and 2 above are ruled out, I need to think of something else...

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Ok, I've made great progress and can see the light at the end of the tunnel!

 

I have the design fully routed except for HDMI and the AVR JTAG pins. That is the task for tomorrow...

 

Here is all layers:

post-29509-0-65605700-1392332760_thumb.p

 

Here is FPGA all routed on the top:

post-29509-0-20411200-1392332778_thumb.p

 

Here is AVR on the bottom:

post-29509-0-89429800-1392332775_thumb.p

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Ok, HDMI is placed and routed.

 

Bottom:

post-29509-0-12271600-1392412814_thumb.p

 

Differential Pairs:

post-29509-0-11907900-1392412813_thumb.p

 

I did the best I could with the differential pairs, its not perfect but if we can get at least 420p or 720i then I think that will be good. Keep in mind that we probably won't have enough memory with the SRAM on this board to do 1080i or 1080p...

 

Jack.

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Ok, I just connected the AVR JTAG pins and now everything is placed and routed and all DRC errors are accounted for!!!!!!!!!!!!!!!!!!!!!!

post-29509-0-46241200-1392414676_thumb.p

 

Next step, verify everything and fix up the silkscreen layers.

 

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