Jack Gassett

The next generation Papilio - help me shape it.

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Jon W,

 

That is food for thought... The SPI Flash chip that we are using allows around 24 bit files which right now seems like a lot but could be a limiting factor pretty soon.

 

Let me think about how feasible it would be to optionally support that.

 

Jack.

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Ok, now that there is a new ZAP IDE release and the Denver Broncos just lost the Super Bowl in embarrassing fashion so I need something to cheer me up it is time to get back to work on this circuit board.

 

First question to ponder, run the ATmega32u4 at 5V or 3.3V? Right now it is setup for 5V operation and since we have series limiting resistors on the D0-D13 pins the FPGA is 5V tolerant. The safest bet is to run the Atmega32u4 at 3.3V... If we do run at 5V then I will need to add series limiting resistors to the ICSP programming pins which are directly connected right now.

post-29509-0-54832000-1391403208.png

 

I think I'll wait for some feedback before making the final decision...

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Next task is to add PMOD support:

post-29509-0-43517200-1391407549_thumb.p

 

Doing so overlapped with one of the holes in the Arduino Mega footprint so it had to be moved. But there were requests for a more standard hole pattern anyway so I moved three of the holes to a standard distance from the corners.

post-29509-0-86107100-1391407649_thumb.p

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Since we have bscan jtag Logic Analyzer mode now there is no real need to connect channel A rx/tx pins directly to the FPGA. This caused problems anyway and would not have worked without some kind of a switch. So I disconnected those pins and we have two free pins now.

 

post-29509-0-37786800-1391408423_thumb.p

 

My first thought for these free pins is to connect 1 more pin on each of the FT2232 channels to allow the FPGA to signal when it is ready to send when it is a slave in SPI mode. The trick is which pin is going to be most beneficial in the other modes... CTS is the most logical pin to connect since it is the functionality I'm actually talking about. Scratch that, we can't use CTS, its already connected as TMS/CS. I usually see DTR used when a pin is hijacked for another purpose. It also has the benefit of being GPIOL0 in MPSSE mode...

post-29509-0-55576100-1391409760_thumb.p

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regarding "standard hole pattern", It's the distance between holes that is important, not distance from the corners.

So if the holes fits on an 5x5mm grid for instance, not sure about others, but i use tamiya plates http://www.pololu.com/product/734 and http://www.pololu.com/product/79

 

Here is the distance between holes in inches:

post-29509-0-83093800-1391409143_thumb.p

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Darn! I just realized that I somehow lost all the HDMI stuff! What the.... Arghhh, have to do it again, I must not have saved it since I was just testing to see how it would look.

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Just added a "Benchy" slide switch from the Seeed open parts library, it is quite large though, it might need to be eliminated or replaced with a surface mount one. This does go against the all surface mount philosophy...

 

post-29509-0-95216300-1391466941.png

post-29509-0-43834100-1391467022_thumb.p

 

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Not to veer too far off topic, but have you tried using Mercurial (or Git) for EAGLE file revision control?
 
And if I understand neslekkim's comment, the holes would be spaced 1.9685" (50mm) or 2.165" (55mm) by 3.74" (95mm) or 3.937" (100mm), right?

Of course, then we'd have to start using A4 paper for documentation... :P

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Ok, now that there is a new ZAP IDE release and the Denver Broncos just lost the Super Bowl in embarrassing fashion so I need something to cheer me up it is time to get back to work on this circuit board.

 

First question to ponder, run the ATmega32u4 at 5V or 3.3V? Right now it is setup for 5V operation and since we have series limiting resistors on the D0-D13 pins the FPGA is 5V tolerant. The safest bet is to run the Atmega32u4 at 3.3V... If we do run at 5V then I will need to add series limiting resistors to the ICSP programming pins which are directly connected right now.

attachicon.gifICSP pins.png

 

I think I'll wait for some feedback before making the final decision...

 

Ok, for now at least, decided to go with 5V and series current limiting resistors.

post-29509-0-42112000-1391533686_thumb.p

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Friendly greetings !

 

I'm still a newbie, i'm very very interested in FPGA, mostly because i'm a sysadmin and i believe in FPGA embedded in a server for some specialised stuff the cpu suck at.

But i'm doing it as a hobby because i don't know any company crazy enough to believe this, so i'm on my own budget :)

 

Being a newbie, what could i say ?

  •  keep it cheap and simple : i never wanted to buy thoses overpriced dev board with tons of stuff i'll probably never need.
  •  Arduino like or arduino compatible shield : Yes thats nice. But ...
  •  I have some arduino shield, including an ethernet shield. can i use it with the papilio pro ? i have no idea, at all.
  •  showcase : i bought the papilio pro as soon as i saw the SID player video. you need as much "cool" showcase as you can :)
  •  ZPUino & AVR : i don't care. probably some people like this.
  •  high speed serial : yesssss pleaaaase ! i don't know if i'll ever need it but that's a good selling point. (the arduino certainly can't do that)
  •  RAM : i don't know if i'll ever need it, i'll probably need it yes. but that's another selling point
  •  hdmi ouput : well... meh. if you can provide well documented, easy-to-use, up-to-date ip core. Sure why not, but the VGA shield seem good enough for me. (i'm not going to plug my fpga board on a high end expensive screen that have only dvi & hdmi)
  •  hdmi input : i, don't, care. if i really want to process image/video, i'll do it using the usb port. or buy a specialised fpga card. (and good luck to get free ip core for video processing)
  •  sram over sdram ? i don't know, i never tried to use the ram ... but i will

 

So, do i really need more stuff on the board ? Nope, not really.

Whatever you do, please keep in mind that it shouldn't be too fragile or, at least, doesn't LOOK too fragile.

 

The major selling point of the arduino is : cheap, easy to use, the shields, and ... gigatoooooooooons of library & endless count of documentation/tutorial.

The major problem with fpga is : very closed system, very very expensive software & ip core.

  1. Arduino got a critical mass were people write bit of documentation here and there, others compile them in something readable, so you'll never be alone as long as you can STFW.
  2. Raspberry pi : mmm.... almost, not sure.
  3. All FPGA boards : lost deep in abyss.

 

Whatever helping to connect to the modern world is good for me. 

VGA : it's ok, no need for hdmi

USB : Yes, of course. best interface, it power the board, it program the board, it can be used to connect to program running on the pc

Audio : Yep

Ethernet : the arduino shield ? or embedded on the board with PoE to power it ?

Other IO : i use my cheap oscillo/logic-analyzer for now

 

What i need, i really need, is : up-to-date documentation, a collection of free ip core. (yes i know, it's the most annoying stuff to do).

And... ho, while i'm here : where is the wiki ?  :huh:

 

Thx  ^_^

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>> The major problem with fpga is : very closed system, very very expensive software & ip core.

got some good news for you: None of that is true. Not anymore.

 

Get the cheapest possible FPGA board - if it has one LED, it's enough. Consider it a write-off, spend some weeks with it and start saving for a bigger board.

If you have the patience and energy, it may be the best investment you've ever made.

 

BTW, the purpose of the abovementioned "bigger board" is solely motivation. For learning, a single LED is enough for a very long time (boils down to "works - doesn't work").

Actually you don't really need the hardware to get started. Download Xilinx ISE 14.7 for free, and it includes everything minus the LED :)

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What i need, i really need, is : up-to-date documentation, a collection of free ip core. (yes i know, it's the most annoying stuff to do).

And... ho, while i'm here : where is the wiki ?  :huh:

 

Thx  ^_^

 

So the whole http://papilio.cc website is a wiki that anyone can edit or contribute to. There is also the new learning website where we will be writing tutorials.

 

For a collection of free ip core - we can do one better. How about a collection of free ip cores that you can use without learning any VHDL? Just use a schematic editor to drag and drop the cores you need and wire them up. That's what our biggest push is right now with the Papilio Schematic Library and is integrated into the latest version of the ZAP IDE.

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For a collection of free ip core - we can do one better. How about a collection of free ip cores that you can use without learning any VHDL? Just use a schematic editor to drag and drop the cores you need and wire them up. That's what our biggest push is right now with the Papilio Schematic Library and is integrated into the latest version of the ZAP IDE.

 

I checked some tutorials about this but i got some problem because of some difference between version of ISE. (where the hell is the library manager now ?  :angry: )

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I'd like to second the call for low-cost boards.

 

I started out as a software guys with hobby electronics background, and I've been keeping a quarter of an eye on FPGAs for a very long time. However, nothing has pushed me into actually learning about them, until I got to an application where the built-in peripherals in an MCU aren't enough -- I need a large amount of quadrature decoders, cheaply, with a very small amount of logic.

Even so, paying the $70 or so for the Papilio One + Logic Start MegaWing was a barrier that kept me away from it for about six months, before I could finally take that plunge.

If the price had been substantially higher -- say, over $89 to get started -- I may never have taken the plunge. Meanwhile, the 250k gate-units in the One 250k is just fine for me; I don't have any plans to take the world by storm with a speculative-execution free CPU core or anything ;-)

 

Personally, I'm not as excited about the Arduino form factor. There are a lot of shields, true, but I find that most of them are not right for my projects. In the low-power MCU world, I'd much rather use a bare, DIP, Atmega, and a soldered breadboard or a quick PCB from some place like OSH Park, to get where I need to go.

Also, the Arduino shields/pinouts are criminally short on GND pins, and also somewhat short on supply pins; for any "real" system you have to break those out using some other method anyway. I find the Papilio wing system to be much better for this purpose, honestly.

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>> because of some difference between version of ISE

 

welcome to EDA tool hell. If it were easy, anybody could do it (took me half a day to figure out that Vivado is the wrong download).

 

>> with a speculative-execution free CPU core or anything

oh I've seen that .. everytime there's a bug in my design and the tool can prove it reduces to a constant. Can software have a sense of sarcasm? Probably yes.

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Ok, the schematic entry is done and everything is connected that we want connected. Now for the hard part, placing and routing the design.

 

The first big question is 4 layers or 2 layers... 4 layers is going to cost twice as much per PCB... For this sized pcb I guess that it will cost about 1-2$ for 500 2 layer boards and $3-4 for 500 4 layer boards. That's just my guess based on previous orders.

 

I studied the design all day today and thought through several routing strategies. I think that I can route everything except the HDMI as a two layer design. The downside is that there will not be an unbroken ground plane below all of the FPGA's GPIO traces so we should not expect solid performance if those traces are used for high speed signals. But the honest truth is that the majority of uses that this board will be put to are not going to use high speed signals... I don't mind dropping HDMI to achieve a 2-layer design, but I don't much like having all of the GPIO traces intersect the Arduino traces. The routing strategy would be all FPGA GPIO would use the top layer and ATmega32u4 and FT2232H traces would use the bottom layer...

 

If I go with 4 layers then there can be a proper ground plane which will eliminate the worry about the traces being used with high speed signals. I think we can also route HDMI... So 4-layers is really the way to go here, but it is much more expensive during the prototyping phase and I would like to get an official quote before committing. I think we can live with $4 PCB cost, but its also important to consider that if this board is not very popular and we only manufacture 100 at a time then we are looking at more like $6 board PCB cost.

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Wow, I totally missed this topic over the last weeks.. lots of good stuff in here.

I thought I'd just share some thoughts on the next design since I really like the platform and I'm thrilled to see it expand with new hardware

 

We have used the Papilio Pro as a controller for a pretty cool project at the company I work for, but our bottleneck performance-wise is the transfer speed on the USB/UART

 

My adventures with the FTDI FT2232H haven't exactly been a dawdle. Using the 245 FIFO mode to get the highest speed on the device uses 15 pins in my latest design. The timing requirements are a real headache (see page 27-28 in http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf ) and even on a Virtex-6 I had to work hard to make it work properly so I just want to make the point that somebody should try to check the timing requirements will be met.

 

If we do not go for full routing for 245 FIFO mode of the FTDI chip, then what speed can we achieve with the device with MPSSE? From what I read on the FTDI website they say that the maximum UART bitrate is 12 Mbaud, but that is limited by the level shifters, which we do not use for FPGA < - > FTDI interface. Does anybody have any data on this, like from Pipistrello or something?

I like the simplicity of using the UART mode since those drivers are easy to use on any operating system and most programming platforms (We use LABVIEW for example).

 

I second Alvie's point on going to faster/bigger DDR RAM chips. For most users this will be completely transparent anyways.

 

Regarding the Arduino footprint I see that it has its advantages. We recently started using the DUE in some of our projects and it's a big step up from the ATMEGA CPUs but still it lacks the versatility of the FPGA I really look for (like adding more SPI interfaces which is pretty easy with the Papilio).

Furthermore the Wings already existing for the Papilio I do not think it is that hard to redo the design of the RetroCade wing to fit the new Papilio IF we don't have to make it compatible with the Arduino's. So on that point I think getting access to the already existing Shields for Arduino is a good thing.

 

Here's another Idea I just thought of, could we make the Papilio dock as a shield on a Arduino MEGA/DUE or is that complete nonsense?

 

I don't have anything against adding an Arduino on the board to get the Analog pins, I think it is a matter of convenience really since the Arduino is well debugged and tested. As long as it is secondary to the FPGA for the primary purpose of adding the analog pins (it would be nice if it were somehow reprogrammable as well when I think about it so that the programmer can customize the functionality, like taking samples at intervals and pushing them to the FPGA for example).

 

 

Those are the things I could think about right now

 

Kalle

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From what I read on the FTDI website they say that the maximum UART bitrate is 12 Mbaud, but that is limited by the level shifters, which we do not use for FPGA < - > FTDI interface. Does anybody have any data on this, like from Pipistrello or something?

 

 

The 12 MBaud limit is set by the baud rate generator, not the level shifters.

 

From the data sheet:

"The Baud Rate Generators provides a x16 or a x10 clock input to the UART‟s from a 120MHz reference clock and consists of a 14 bit prescaler and 4 register bits which

provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 183 baud to 12 million baud.
The FT2232H does not support the baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud"
.

Magnus

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