Chris_C

implementing a truth table in vhdl?

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as the title, adverse to wizards like to understand what I'm producing! I'm using a pap pro not that that should make too much difference, but in future could be using much smaller and also larger fpga's...

would prefer something less verbose that a select statement!

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There's nothing wrong with a case or select statement. Even if you think it's too verbose, this doesn't matter during synthesis as it will be optimized to the best representation using the right FPGA block. You haven't really given us much to go on, what truth table, how many inputs etc. Some very large and complex tables can be implemented as ROMs, other medium ones you can use case statements and the real trivial ones you can just use a few lines of combinational logic or if then else statements.

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well I've groked over the last 30 years, so many languages that symantically that structure to me is a select clause! - I forget sometimes that the rest of the world doesn't speak my internal object oriented language :wacko:

 

You have however comprehensivly answered my question by the looks of it (thanks for the sanity check!)

 

If I understood you...

 

basically if I want a simple ALU or simple ROM microcode table - I'd just implement a ROM (as much I suspected) and for trivial stuff just bang out a CASE, statement...

 

for something really convoluted or that needs to be more easily understood six months (or more) down the line then I may be better off with combination logic / if then else ...

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You might also be able to do something like this (haven't tested it though...)

 

constant truth_table :std_logic_vector(3 down to 0) := "1000";

 

result <= truth_table(conv_integer( unsigned( a & b ));

A bit short and ugly though...

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You might also be able to do something like this (haven't tested it though...)

 

constant truth_table :std_logic_vector(3 down to 0) := "1000";

 

result <= truth_table(conv_integer( unsigned( a & b ));

A bit short and ugly though...

 

This is a 1 bit ROM implementation. Its the same pattern you use to make ROM but with a std_logic_vector instead of an array of them and the input bits concatenated rather than an address.

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