tmorkus

IP core generation problem

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Hi,

 

I am new there, I'm just learning using Papilio Pro and the Hamster's book, so please forgive me if this is some beginners mistake ;-)

I have problems with generation Block Memory as described in the Chapter 15 of this book - I get following error message:

 

ERROR:sim:938 - Error while preparing for IP customization
ERROR:sim - Failed to initialize IP model.
ERROR:sim:944 - Failed to generate ASY schematic symbol.
ERROR:sim - Failed to generate 'memory'.  Failed to initialise IP Model for ASY schematic symbol
 
Using ISE 14.7 under Linux 64 bit (Ubuntu 12.04). I tried also ISE 14.4 before, but there were no IP cores for Spartan 6 xc6slx9-2tqg144.
 
Please, can anybody help?
 
Thank you.
 
Tomas

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Now I created the IP core different way: "Tools->Core Generator". There I changed "Project options" : unselect the "ASY Symbol File". Then I was able to renerate the block RAM and add them to my project. But when generation bit file: I get this error message:

 

WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.
 
But the bit file is generated and seems to be working. Should I ignore this warning?
 
Thanks,
 
Tomas

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I'm not sure what that error message means, never seen it before, but if you are dealing with VHDL then you can safely uncheck the option to generate a symbol, the symbol is for use in the schematic editor so will be of no use to you anyway.

 

Jack.

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I see, OK, I'll uncheck the option, I am learning VHDL only.  May I have once more question regarding ISE? Which version of ISE you recommend to use for Papilio Pro?

 

Thank you,

Tomas

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Tomas,

 

I always go with the latest version, they are usually very good about not releasing a lemon. There was only once a couple years ago where there was a version to avoid, but I think they learned from that and it has always been the right approach to use the latest version.

 

I'd be more concerned about the linux version of the software then the latest version. I've seen weird stuff using the linux version and I suspect the error you are seeing is something weird with the linux version... But if you have a workaround then it should be good.

 

Jack.

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Hi Jack,

 

I'll try the same VHDL code under Win7/64bit, but I dyslike Windows and try to avoid using them. Just for curiosity :-) I thought that the base of the ISE is the same under both OSes.

 

BTW: I appreciate, that also your software is for Linux as well - most but the ZAP IDE.

 

Tomas.

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They are supposed to be the same for both OSes, but I always find goofy stuff when I test under linux...

 

The ZAP IDE does work under linux, we just need to make an official linux release.

 

Jack.

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Hi Jack,

 

I found much better workaroung for IP core generation under Linux - no need to disable ASY. I hope, that this may help somebody other as well.

 

- don't use "New Source" from Design tab for IP core generator at all. Instead go directly to "Tools -> Core Generator "

- select "File -> New Project", and set name to the project (or let the standard coregen.cgp)

- then select "Project Options" to Spartan6, xc6slx9, tqg144, -2

- select the IP core from the menu list and generate them standard way, no need to disable ASY generation

- close the "Core Generator" window

- then in Design tab add a new source to the project select "Add source", select "ipcore_dir" and then select the generated IP core, "OK"

- and that's all folks, everything seems to work correctly.

 

If there are existing IP cores, there is no need to add new project, just add the IP core via "Tools -> Core Generator ", not from the Design tab.

Also further changes to IP core (e.g.) add the *.coe has to be also done via "Tools -> Core Generator ".

 

BTW: This is a great news about the ZAP IDE, hope, that the official release will be available soon

 

Tomas.

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Hi,

 

maybe inference is less of a hassle than creating RAM with the core generator.

You write Verilog (VHDL) code that describes a RAM, and the tool maps it automagically to hardware RAM blocks. The nice thing about it is that it's vendor-independent.

 

An example can be found here:

http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/

I happen to have an example project (for Papilio pro; uses an inferred RAM as FIFO and prints @ABC@ABC@ABC... via USB serial port at 9600 baud)

https://drive.google.com/file/d/0B1gLUU8hXL7vbFdtQjNLVmFuM28/edit?usp=sharing

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note to self:

http://www.xilinx.com/Attachment/Xilinx_Answer_46945_Data2Mem_Usage_and_Debugging_Guide.pdf

 

One problem with inferred ram seems to be that the tool uses parity bits and uses 9+9+9+5 bits for a 32 bit memory.

Makes the .bmm file more interesting... It should be straightforward but I haven't gotten it to work yet with a zpu.

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(I understand that this is an older topic)

Because I ran into the same ASY file generation error as the original issue reported by Thomas, and because I'm running ISE on linux too, I searched for more info.

 

Xylinx has accepted this as a known issue related to linux for non-US environments, and explain how you can set the environment to make it work.

I'm going to try if I can fix it just by setting my decimal separator to dot in stead of comma...

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I can confirm that the original reported problem is resolved by setting the following variable:

LC_NUMERIC=en_US.UTF-8

 

In my profile this was set to

nl_BE.UTF-8

(because I'm from Belgium and my language is dutch, so that makes some sense  :)  )

 

I did this as a permanent setting  by changing my $HOME/.pam_environment file, and loging out and in to linux again.

 

Results in ISE when adding a Single ROM  memory component:

Generating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol....Wrote CGP file for project 'memory'.Core Generator create command completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "/home/jan/papilio/memorytest/ipcore_dir/memory.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.

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