Chris_C

isim time base

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I'm messing with clocks and counters...

 

I can change the total time isim runs for but I don't need resolution down to 1uS

 

also should I remove things like counters which will be running higher than the resolution I'm wanting to look at?

 

 

I'm using a counter to reduce the frequency of the clock to something human noticable so say 1/2 second obviously if I plot 2 seconds at 1uS I'm gonna get waaay too much data!

 

I haven't even got my mits on the hardware and already I'm enjoying fpga's - to think I put this off for ages while always wanting to get into it... go figure...

 

 

 

 

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I'm using a counter to reduce the frequency of the clock to something human noticable so say 1/2 second obviously if I plot 2 seconds at 1uS I'm gonna get waaay too much data!

 

So zoom out in isim until you have one second range on the screen. Otherwise, if you really really must mess around with the time scale use the -timeprecision_vhdl 1ms command or somesuch but if you don't really understand the effects it can have you may end up with incorrect simulation results.

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It's taking way too long to produce a graph of 2 seconds at 1uS, hence zooming isn't really practical, but I'll certainly give your -timeprecision_vhdl 1ms a go, thanks

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You're also probably doing it wrong. On a FPGA, you have no choice but to take the fast clock and divide it down to a very very slow one if your logic runs super slow.

 

However if you separate your clock from the rest of the logic, you can simulate that logic and have your test bench provide the slow clock directly to your logic module. That way you no longer have to simulate a fast clock into a big counter divider. Your simulation will run lightning fast with default settings. Hope that makes sense.

 

Here's an example:

architecture behavior of test_tb is   signal sloooow_clk  : std_logic := '0';   constant clk_period : time := 500 ms;begin   uut: entity work.my_widget_under_test_that_requires_slow_clock   port map (     clk => sloooow_clk--   blah_port => blah1,--   bloh_port => blah2,--   bleh_port => blah3,   );          clk_process :process   begin        wait for clk_period/2;        sloooow_clk <= not sloooow_clk;   end process;

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alas with that setting I get no traces...

 

but I see what you're getting - as long as I can be sure the down counter is working - I can basically ignore it and run the sim at any speed...

thanks

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