Wile_E_Coyote

Intro To Spartan FPGA Book Error

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So, I was going through the "Intro to Spartan FPGA Book" to get familiar with FPGA coding, and I got stuck on the "Addition and Subtraction, The Hard Way" section (Chapter 9).  I put in the example code that was given in the book, but when I went to extrapolate the code to calculate 4 bits addition and subtraction, I did not get the expected results.

 

So, here's what the example code in the book gives:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Switches_LEDs is	Port ( 	switches : in STD_LOGIC_VECTOR(7 downto 0);		LEDs : out STD_LOGIC_VECTOR(7 downto 0));end Switches_LEDs;architecture Behavioral of Switches_LEDs is	signal x 	: STD_LOGIC_VECTOR(3 downto 0);	signal y 	: STD_LOGIC_VECTOR(3 downto 0);	signal carry 	: STD_LOGIC_VECTOR(3 downto 0);	signal result 	: STD_LOGIC_VECTOR(4 downto 0);begin	LEDs 		<= "000" & result;	x 		<= switches(3 downto 0);	y 		<= switches(7 downto 4);		result(0) 	<= x(0) XOR y(0);	carry(0) 	<= x(0) AND y(0);		result(1) 	<= x(1) XOR y(1) XOR carry(0);	carry(1) 	<= (x(1) AND y(1)) OR (carry(0) AND X(1)) OR (carry(0) AND Y(1));end Behavioral;

This code is wrong...that is to say, it is incomplete.

 

When you add the following two binary numbers, this is what you get:

 

  11

+11

-----

110

 

In other words, 3 + 3 is 6, which is what is defined above.

 

So, based on the code above, "result(1)" is x(1) XOR y(1) XOR carry(0).  Let's examine this in a little more detail...

 

Result(1) above is the result of adding x(1), y(1), and carry(0).  Now, it is true that what was provided in the book does, in fact, cover one of the conditions; however, if you add 1 + 1 + 1, you get 3, which is a binary 11.  So that means that there is another condition where you could get a "1" in the result and a "1" in the carry.  When we have "another" condition, the best way to describe it is with an "OR" function.

 

This is the code I wrote that actually adds up correctly:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Switches_LEDs is    Port ( LED		: out	STD_LOGIC_VECTOR (7 downto 0);           Switch 	: in  	STD_LOGIC_VECTOR (7 downto 0));end Switches_LEDs;architecture Behavioral of Switches_LEDs is	signal	x	:	STD_LOGIC_VECTOR (3 downto 0);	signal	y	:	STD_LOGIC_VECTOR (3 downto 0);	signal	carry	:	STD_LOGIC_VECTOR (3 downto 0);	signal	result	:	STD_LOGIC_VECTOR (4 downto 0);begin	LED		<=	"000" & result;	x		<=	Switch (3 downto 0);	y		<=	Switch (7 downto 4);		result(0)	<=	x(0) XOR y(0);	carry(0)	<=	x(0) AND y(0);		result(1)	<=	(x(1) XOR y(1) XOR carry(0)) OR (x(1) AND y(1) AND carry(0));	carry(1)	<=	(x(1) AND y(1)) OR (carry(0) AND x(1)) OR (carry(0) AND y(1));		result(2)	<=	(x(2) XOR y(2) XOR carry(1)) OR (x(2) AND y(2) AND carry(1));	carry(2)	<=	(x(2) AND y(2)) OR (carry(1) AND x(2)) OR (carry(1) AND y(2));		result(3)	<=	(x(3) XOR y(3) XOR carry(2)) OR (x(3) AND y(3) AND carry(2));	carry(3)	<=	(x(3) AND y(3)) OR (carry(2) AND x(3)) OR (carry(2) AND y(3));		result(4)	<=	carry(3);end Behavioral;

Using the above code, I went through every possible addition scenario and it adds up correctly.

 

Hope this helps!

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So, based on the code above, "result(1)" is x(1) XOR y(1) XOR carry(0).  Let's examine this in a little more detail...

 

Result(1) above is the result of adding x(1), y(1), and carry(0).  Now, it is true that what was provided in the book does, in fact, cover one of the conditions; however, if you add 1 + 1 + 1, you get 3, which is a binary 11.  So that means that there is another condition where you could get a "1" in the result and a "1" in the carry.  When we have "another" condition, the best way to describe it is with an "OR" function.

 

I believe you are mistaken, if both x(1), y(1) and carry(0) are all '1' then the result(1) expression resolves to '1' XOR '1' XOR '1', in VHDL results are calculated left to right so this is actually ('1' XOR '1') XOR '1' which comes out to '0' XOR '1' which is easily seen to be '1', thus the expression for result(1) is correct if we have a '1' in both inputs and the carry in, the carry logic then deals with providing the carry out bit for all cases, which gives the other '1' from your example.

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Wouldn't VHDL '1' XOR '1' XOR '1' simply build a three-input XOR gate? The results I was getting seemed to suggest this. The circuit was not resolving three '1's into a '1' for the result and a '1' for the carry...it was, however, resolving to a '0' for the result and a '1' for the carry.

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It did.

entity Switches_LEDs is    Port ( LED 		: out	STD_LOGIC_VECTOR (7 downto 0);           Switch 	: in  	STD_LOGIC_VECTOR (7 downto 0));end Switches_LEDs;architecture Behavioral of Switches_LEDs is	signal	x	:	STD_LOGIC_VECTOR (3 downto 0);	signal	y	:	STD_LOGIC_VECTOR (3 downto 0);	signal	carry	:	STD_LOGIC_VECTOR (3 downto 0);	signal	result	:	STD_LOGIC_VECTOR (4 downto 0);begin	LED	<=	"000" & result;	x	<=	Switch (3 downto 0);	y	<=	Switch (7 downto 4);		result(0)	<=	x(0) XOR y(0);	carry(0)	<=	x(0) AND y(0);		result(1)	<=	(x(1) XOR y(1)) XOR carry(0);--) OR (x(1) AND y(1) AND carry(0));	carry(1)	<=	(x(1) AND y(1)) OR (carry(0) AND x(1)) OR (carry(0) AND y(1));		result(2)	<=	(x(2) XOR y(2)) XOR carry(1);--) OR (x(2) AND y(2) AND carry(1));	carry(2)	<=	(x(2) AND y(2)) OR (carry(1) AND x(2)) OR (carry(1) AND y(2));		result(3)	<=	(x(3) XOR y(3)) XOR carry(2);--) OR (x(3) AND y(3) AND carry(2));	carry(3)	<=	(x(3) AND y(3)) OR (carry(2) AND x(3)) OR (carry(2) AND y(3));		result(4)	<=	carry(3);end Behavioral;

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I tested a simple module that had 3 inputs and one output, which just did output <= in1 xor in2 xor in3;

And when I forced all the inputs to '1' in the simulator the output was '1'.

 

It doesn't matter if it is a 3-input XOR gate or a cascaded series of XOR gates as XOR is a linear operation.  In general XOR outputs '1' if there is an odd number of '1' inputs and '0' otherwise, so if you are seeing other behaviour then something is wrong.

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