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Using Papilio One as logic analyzer

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I am trying to use papilio one as a logic analyser. However everytime I try to connect to it using Jawis client it says "Device not found". Could someone please help me out ? Baud rate is 115200

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Can you give us more details? Where are you downloading the Logic Analyzer project from? What do you see when it loads the LA bit file to the Papilio board etc.

 

Jack.

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It successfully uploads to the board. But when I try to connect to it it says no reply from device. Do I need to buy extra wings of some sort to connect to the serial ? Or is it the defualt USB to Serial which it uses? Is there a wiki for this anywhere?

Also I am writing to the SPI flash of the Papilio

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Ok, thats the problem. Please be aware that the content at gadgetforge is just there for archiving reasons, everything there is old. That version did not run at 115000, it only worked at 38K.

 

There was a bug that I had to track down in order for Sump to work at 115000 with the FTDI chip. The latest code is located here:

http://forum.gadgetfactory.net/index.php?/files/file/11-sump-logic-analyzer/

 

Jack.

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Something else to check is make sure the VCP checkbox is selected under the USB to serial converter in the device manager, at least in Windows. For some reason on mine this was not selected by default so I got no serial port.

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Thanks. With the latest code I am able to open the device at 115000 baud rate. However I am unable to find out which channel maps to the physical pins on papilio. Can you send the link for the mapping of pins ?

When I set 100MHz sample rate the capture gets completed in 2.53s. Is this expected ?

Does the code forward the date to sniffer or does it store it and then forward it ? Basically I would like to know whether there is any memory limitation ?

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Maybe the above mail was not clear. I would like to know the pins to which I can connect the trigger signals. Right now I am not able to see any toggling on any of the channels

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Sorry for the delayed response, I have not touched the Logic Analyzer code in years so I don't remember off the top of my head how it was configured. I had to fire it up and poke around to get the info you need. Please keep in mind that this project was just an afterthought from the work I did with the OpenBench Logic Sniffer. If you want an actual well documented Logic Analyzer then that is where I put all of my effort.

 

Having said that, it is one of my goals to put together a new version of this that will be paired with the ZPUino and will include new features like signal generator and other cool features. But I have to get the Papilio Schematic Library up and running first. Then the new system will be built using the PSL so anyone can modify it.

 

I just fired it up on a P1 500K and connected one end of a jumper wire to 3.3V and the other end to the various inputs on the Papilio. It looks like Row A 0-15 correspond to the channels 0-15 of the Logic Analyzer and Row C 0-15 correspond to channels 16-31. You should be able to walk your jumper wire that is connected to 3.3V down the rows and see the logic level show up as high when you do a capture.

 

There is 24Kb of memory available, if you set the memory to Automatic the memory will be automatically allocated between all the channels. If you just need to capture a couple signals then just use channel group 0 and uncheck channel groups 1,2,and 3. This will allocate all 24Kb to 8 bits so you will get more memory available to you then if you had all 32 channels enabled.

 

Jack.

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THanks Jack. I could connect VDD and see the level change in the channels. But my debugging of SPI is not working. Still looking into it. WIll get back if I need more help. Thanks again

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