bleedinggums

ERROR:Place:1018

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hi!

 

i bought the papilio mainly because i want to use it in my product. one of my product requires a deserialiser. the fpga seems perfect for this application. i went for papilio as i wanted to use port c for the input data and use ports a and b to output data in parallel.

 

 

however, i encountered some problems using it.

 

first of all, when i want to create the design, i get this pesky error message.

 

" ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /clock site pair."

 

my signal consists of BitClock, Data and etc. the data will synchronise with BCLK. i wanted to use P98 as BitClock. naturally my program works on "rising_edge(BCLK)". but it seems i can't use P98 for this purpose.

i tried a few other pins and it seems i keep on getting other errors related to my choice of pin for BitClock. 

any suggestion here?

 

thx!

 

bg

ps: i scoped and i can't get any output at all. i suspect it's related to this 1018 error.

 

 

 

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Try choosing a GCLK input for your clock. If you can not, there are some options like "CLOCK_DEDICATED_ROUTE" that can help with that.

How fast is your input clock ? If it's significantly slower than the internal FPGA clock, you can try to sample it instead.

 

Also - make sure your design is adding the input clock buffer (IBUFG).

 

I cannot help you any further unless you specify which papilio you're using. And if you can, please state the clock speed you need - different clock speeds might require different approaches.

 

Best,

Alvie

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hi alvie

 

thx for replying.

 

the signal is only 5 mhz. so it's not very fast. i don't understand what do you mean by choosing a GCLK input for my clock? how do i do this?

 

i also don' know about adding the input clock buffer.

 

sorry, first time using fpga here.

 

i'm using papilio one 250k.

 

bg

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GCLK means Global Clock. Only certain pins on the FPGA support GCLK meaning they are able to route the external clock signal to internal global clock distribution networks. You need to go to xilinx.com and look at the very useful documentation they have on their FPGAs including pinouts that will tell you which pins support GCLK. I'm guessing you might need to look at document ds160 for pinouts.

 

As for not knowing how to add the input clock buffer, I recommend reading Xilinx Spartan-6 Libraries Guide for HDL Designs and have that as your reference bible. All the primitives you could possibly want to use are described in there. Look for IBUFG.

 

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If using VHDL, add these at the top

 

  library UNISIM;
  use UNISIM.VComponents.all;

 

And then add the buffer:

 

  BUFG_clock : BUFG port map ( I => clock_unbuffered, O => clock);

 

where clock_unbuffered is the raw pin.

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You sure :) ?  From the manual, emphasis mine.

 

BUFG is a high-fanout buffer that connects signals to the global routing resources for low skew distribution of the signal.
IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGA's global clock routing resources. 

 

So long story short, if you have a DCM or PLL and synthesizing a clock signal internally to the FPGA and you want to distribute it globally use a BUFG, if you have a clock generated externally to the FPGA and applied to one of its pins use a IBUFG.

 

But yeah, the rest of the VHDL is solid, use that. If you actually read through the HDL design doc I posted a link to above, it even gives you instantiation templates for each of the components in both VHDL and Verilog, makes it as easy as copy paste, to implement them.

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Nah, never sure - I make this up as I go along!

 

Given that he might not have been on an global clock pin (maybe needed CLOCK_DEDICATED_ROUTE and all that jazz) I was playing it safe - as long as it gets into the FPGA fabric it might fix the problem. However you are right that there will be a lot of skew in doing this.

 

Mike

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For a 5MHz signal, I definitely would sample it instead of routing it. But since that might be a bit complex, let's see what we can do.

 

See DS312 http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf‎, start on page 174 and identify the possible GCLK pins. Then use the Papilio UCF file to see where (and if) those pins map to the wings. The xc3s500  it's identical to xc3s250 in the TQ144 package.

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hi guys

 

thanks for the comments.

 

i checked out the pdf file and found that i could use pin 91 as it is also a GCLK pin. hardware wise, i just have to solder a jumper wire to it. awesome!

 

now there is no more that pesky error message. however, i'm still not getting any output. 

 

i suspect it is my vhdl coding now. as this is just a deserializer, i'm wondering what could go wrong? it should be quite straightforward. 

 

sorry, obviously i'm not very good at this. appreciate if anyone could take a look at my code.

 

thx!

 

bg

 

DAC.vhd

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I would recommend you learn how to use the simulator. It has proven invaluable for me in the past. From memory, right click in your project, add new file, select VHDL testbench, select a directory to add it to, select your top level module and it's done. In your project, click the simulation radio button at top left, open the new file that was created, usually you have to tidy up the clock as it's not always automatically identified, also change the clock period to mach your real clock timing. From here, you're ready to run a simulation (expand and double click the options at bottom left).

 

With the simulator it's like having a logic analyser with hundreds of channels that can see all your signals in the project simultaneously so you can see what everything is doing and why things aren't working as they should. While in ISIM, you can expand your project tree on the left and drag the module you're interested in into the wave window and an all the signals will be added, or you can just select only the signals you're interested in and just add those. You can then run a simulation, either by clicking the buttons at the top or I just type in the command window at the bottom, eg "run 10ns" with run the simulation for 10 nanoseconds, similarly "run 6ms" etc. If a simulation seems to run too long, control C will break out of it. Give this a try.

 

EDIT: I should also say you probably need to add to your default testbench something to drive the signals otherwise the simulation won't show you much.

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Fully agree with Alex, Was up early this morning (again!) so had a look at it too.

 

It looks like you need 17 or so clocks for each change of WS, also the DATA that is presented when WS toggles is ignored. 

 

if rising_edge(BCLK) then
   if (WS /= current_lr ) then -- change of channel 
      current_lr <= WS; -- initialize
      counter <= width; -- initialize
      R <= Rbuffer;
      L <= Lbuffer;
      shift_reg <= (others => '0'); -- initialize to zero
      ----------------------------------------------------
      -- Maybe it should be also have, depending on timing
       ----------------------------------------------------
      shift_reg(0) <= DATA;      
   elsif counter /= 0 then
      if counter = 1 then 
         ----------------------------------------------------
         -- At the point we have enough data to set the output
         -- to its final state.
        if (current_lr = '1' ) then
           Rbuffer <= shift_reg(width-2 downto 0) & DATA;
        else 
           Lbuffer <= shift_reg(width-2 downto 0) & DATA;
        end if;
      end if;
      shift_reg <= shift_reg(width-2 downto 0) & DATA;
      counter <= counter-1;
   end if;
end if;
 

You should also try to simulate that. However, maybe you are over-thinking it. If you were to change your logic to

 

  When WS changes, the last 16 values of DATA should be assigned to the opposite of what WS currently is.

 

Then a lot of the tricky bits disappear.

 

 
 
architecture Behavioral of DAC is
   signal ws_last : STD_LOGIC;
   signal shift_reg : STD_LOGIC_VECTOR(width-1 downto 0);
begin
   my_process: process( BCLK )
   begin      
      if rising_edge(BCLK) then
         if (WS /= ws_last ) then      -- change of channel 
            if ws_last = '1' then
               R <= shift_reg;
            else
               L <= shift_reg;
            end if;
         end if;
         ws_last <= WS;
         shift_reg <= shift_reg(width-2 downto 0) & DATA;
      end if;
   end process;   
end Behavioral;

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hi guys

 

thanks to everyone who replied on this thread.

 

the simulator is AWESOME!!!

 

took me a while to get going, then only i realised the fun of it!

 

most of the logic is what i want, which is nice but... how come i'm not getting any output?

 

i'll try to scope the outputs again.

 

thx again for the help!

 

bg

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bg,

 

In my experience, when everything works in the simulator but does not work on actual hardware it is often because a latch was inferred instead of a register. It's worth taking a look at the output from your synthesis and see if it says anything about a latch anywhere. If it does research that piece of code and change it until there are no latches.

 

Jack.

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I can't count the number of times that a warning was actually of some value, but was lost in the amazing level of non-issues... 

 

Another good place to start is with pinout report. Check that all the signals are "located" on the desired pin. If any say "unlocated" then they are wired at random!

 

I forget to add a "LOC" contraint for the clock signals all the time. Makes a project very hard to debug when they do absolutely nothing!

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hi jack

 

thanks for your reply. err, could you speak in english please?  :)

 

i checked the synthesis report, it says 

 

summary:

     inferred     1 counter

     inferred     81 d-type flip flops

     inferred      1 comparator

 

so i thought i'm good but as i scroll down the report, in the advanced hdl synthesis report section, i see

 

# counters                     1

  5 bit down counter      1

# registers                      81

  flip flops                       81

# comparators                1

 5 bit comparator  greater   1

# xors                               1

  1 bit xor2                      1

 

but then i think i need flip flops in the design, since it's a simple deserialiser. my code is very simple as shown above, no?

 

hi hamsters

 

in my constraints file, all my signals are defined as 

NET BCLK LOC = "P91" | IOSTANDARD = LVTTL;

 

i guess this is okay?

 

thx!

 

bg

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bg,

 

Sorry about that, I could have been a bit clearer. :) I get typing too fast sometimes.

 

It looks like you are good, you want d-type flip flops ( data-type flip flops, i.e. registers) instead of latches. Both serve the same function, storing data, but FPGA's have d-type flip flops and not latches so if you ever see anything in a synthesis report that says a latch was inferred then that is a big red flag. I didn't know that when I first started with VHDL, if someone would have told me that in the beginning it would have saved me lots of troubleshooting. :)

Jack.

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hi guys

 

what a day!

 

i scoped the signals again, either way with earlier or later version of my program, i should get some signal as my simulation shows. still nothing.

 

so i took a step back and since i have the logic start megawing, i tried out the led switches program using switch 0 and 1 (p3/4) to turn on/off led 0 and 1 (p16/17). guess what? nothing happened!

 

so i suspect this is not an issue with my code. maybe it's in the programming process? or my pc? when we download the program to the fpga, it's just the bit file and nothing else right?

 

i'm using windows 7, the 64bit ise project navigator. 

 

appreciate if anyone has any input on this. thx!

 

bg

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Are you sure that you have set the correct target device for the project? If you like email me the project (run project/cleanup files first) and I willl look at it for you.

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wait a minute!

 

i tried the whole rigmarole again. i realised after writing to the fpga, the program works right away! but after it loses power (like i plug/unplug the usb cable), i seem to have lost everything.

 

is this the reason? because previously i have taken out the unit and power it on again.

 

uh oh, i must have done something wrong here! guess i have to program hex file instead? or i should ask, how do i store the program on the papilio one board so that the program could run every time it is powered up?

 

bg

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bg,

 

If you program to the FPGA then it just sends the bit file over JTAG directly to the FPGA and when power is cycled the bit file is gone. If you want the bit file to be persistent then you need to choose, "SPI Flash" from the Papilio Loader GUI. This will send the bit file to SPI flash instead of the FPGA and whenever power is applied the FPGA will pull its configuration bit file from the SPI Flash.

 

Jack.

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oh no, i seemed to have goofed up again.

 

now for some reasons, i could only generate the bit files but i can't generate the bmm file. how do i generate the bmm file? i looked around, everywhere it says xilinx should build it automatically but i don't see it.

 

appreciate the help. thx!

 

bg

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bg,

 

You shouldn't need to worry about a bmm file. It is only used if you want to use data2mem to merge data into BRAM (Block RAM). It doesn't sound like you need to do that from what you have already posted. Programming a bit file to SPI Flash does not require a bmm file.

 

Jack.

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hi jack

 

i don't need the bmm file? i program the bit file to spi flash, nothing happens.

 

when i had the bmm file, i program both bit and bmm file to spi flash, the program managed to stay there and i was able to execute my led switches program after power off.

 

where did i go wrong?

 

bg

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