Puskyer

New to this tech.

Recommended Posts

Thanks @rdww60...

 

 

also got my Papilio Arcade MegaWing working..

 

trying eh invaders_papilio_pro_Arcade_MegaWing.xise but seem to be missing components.

 

source/plx_arcade_megawing.ucf

build/ipcore_dir/delclk.xco

build/ipcore_dir/delclk.xise

 

but I did get pacman_ppro_lx9 to work.

 

still learning and trying things..

Share this post


Link to post
Share on other sites

Hello @alex

 

yes I am finding that out, I seem to be able to compile to projects but only get black screen because I do not have the roms? will need to see how to get some to test..

 

Will follow your link and see what I find.. thanks..

Share this post


Link to post
Share on other sites

The SHA1 sums of all the ROMs required are listed in the batch files that build the VHDL files from the binary ROM code. This way you can verify that you have the correct ROMs in the correct place. The file naming convention for the ROM files follows MAME so there should be no need to change anything, just unzip the ROM files in that directory.

Share this post


Link to post
Share on other sites

ok confused again..

 

One of the projects from the link zx-spectrum-48k-fpga seems to have a papilio flavor but it is for the Plus not the Pro??

 

can't find much relating to the specs for the plus but it must be bigger them the pro, I get errors compiling the project.

 

ERROR:Place:836 - Not enough free sites available for the components of the
   following type(s).
ERROR:Place:375 - The design does not fit in device.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
 
is the Plus newer then the Pro? I thought the Pro was the big one??

Share this post


Link to post
Share on other sites

The SHA1 sums of all the ROMs required are listed in the batch files that build the VHDL files from the binary ROM code. This way you can verify that you have the correct ROMs in the correct place. The file naming convention for the ROM files follows MAME so there should be no need to change anything, just unzip the ROM files in that directory.

 

will need to find rom's first, have not found them yet so I am trying other projects for now..

Share this post


Link to post
Share on other sites

No the Plus was a short run prototype and never got sold through the shop. It is the same FPGA as the Pro but with static RAM instead of DRAM. Make sure you open the project zx_spectrum_48k_papilio_VGA.xise rather than creating your own project and adding the source files. Everything on my code repository compiles correctly with the provided project files. The pinouts for the signals between the Pro and Plus are different so you have to tweak the .ucf accordingly otherwise if you upload the bit file to the FPGA it won't work.

 

For the ROMs, you have to google for MAME roms. It's not really that hard to get them.

Share this post


Link to post
Share on other sites

Hi @alex

 

did load the zx_spectrum_48k_papilio_VGA.xise under the trunk folder.  went to the "Generate Programming File" right clicked and did "Rerun all" sill get the errors.. will revert to your SVN and try again..

 

 

Pasquale

 

 

also have not modified the ucf file yet, just want to make sure it builds first..

 

Cheers...

Edited by Jack Gassett
Please no posting to ROM sites.

Share this post


Link to post
Share on other sites

just did an

 

svn revert 

then reloaded the  zx_spectrum_48k_papilio_VGA.xise

 

ran each stage one at a time and got the error during the "Generate Post-Map Static Timing" see error below

 

 

Place:836 - Not enough free sites available for the components of the following type(s).
   LUTM   Number of Components 4168   Number of Sites 2880
Place:375 - The design does not fit in device.
 Total LUT Utilization      : 7832 out of 11440
 LUTs used as Logic         : 3664
 LUTs used as Memory        : 4168
 FF Utilization             : 565 out of 11440
 
 
 
not sure if that tell you anything, I am not sure what it means. what are sites?? the errors are around
 
ERROR:Place:836 - Not enough free sites available for the components of the
   following type(s).
 
How do I check how many my Paplilio Pro has?
 
 
 

 

 

update: also found this in one of the map reports??

 

Number used as Memory:                   2,084 out of   1,440  144% (OVERMAPPED)
      Number used as Dual Port RAM:             36
        Number using O6 output only:             4
        Number using O5 output only:             4
        Number using O5 and O6:                 28
      Number used as Single Port RAM:        2,048
        Number using O6 output only:         2,048
        Number using O5 output only:             0
        Number using O5 and O6:                  0
      Number used as Shift Register:             0
 
not sure why I am over mapping?

Share this post


Link to post
Share on other sites

@alex

 

does this help to explain why I am having  problems..

 

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o PAPILIO_TOP_map.ncd PAPILIO_TOP.ngd
PAPILIO_TOP.pcf 
Target Device  : xc6slx9
Target Package : tqg144
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Sun Dec 08 21:06:12 2013
 
going to run it on my Linux version and see if it too has the errors, moved to windows because most of the tools seem to be windows oriented.
 
UPDATE: no same error on Ubuntu 12.04 and 14.7 of the ISE Design Suite?? That is it for tonight....
 
Cheers,

Share this post


Link to post
Share on other sites

Puskyer,

 

I took a look at the repository for  zx_spectrum_48k_papilio_VGA :

 

In the readme file it mentions 

 

"zx_spectrum_48k_papilio_VGA : for Papilio Pro with Arcade MegaWing. Because the external DRAM of the Papilio Pro is not used and there is not enough RAMB internal to the FPGA, this configuration of Spectrum only has 32K RAM. To do so, and in order for the project to synthesize, in file ram.v change

reg [7:0] sram [0:32767]; to reg [7:0] sram [0:16387];

"

 

Maybe this is the issue you are running into. It appears from your log that it is not finding enough sites(slices with FF) in the FPGA

to put together the memory needed.

Share this post


Link to post
Share on other sites

rpflaum

 

thanks, should of gone looking.. found the following in the ram.v

 

reg [7:0] sram [0:32767]; // use 16383 if synthesis fails due to not enough FPGA resources

 

if I had gone looking I would have see it.. although I do not know what the slices with FF stands for... now on to modifying the ucf file for papilio pro..

 

thanks again...

Share this post


Link to post
Share on other sites

Check Table 1 in the documentation sum up ressource of the chip chip.

 

http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf

 

The HW description (the vhdl or verilog code) take too many ressource : The tool was not able to find the ressource to map your HW description on the HW ressource available.

In your case it seems that you request a so big memory that the dedicated memory ressource in the fpga Block RAM (BRAM) wasn't enough. So the tool try to complete doing the memory with remaining flipflop ressources. But it failed claiming the lack of ressource.

 

You can see in the Table 1 of the documentation that by choosing a bigger spartan6 fpga at some point the mapping would pass.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now