F6EEQ

Encoder tests

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I tried the rotary encoder example from XILINX and I found a curious problem.

 

I had my LS normally plugged, and I linked the encoder wires to the VGA plug because this was the only outlet easily available (on VSync and HSync) and they were pulled up high via the UCF config.

It did not work.

So after hard :P thinking, I decide to slide the LS in the "led and switch only" position on wing C, and to connect the encoder to some place in the free wing, UCF adapted but everything remaining the same.

Suddenly everything was running well.

 

I suppose the 2 serial resistors in the VGA connection (82 ohms) although small brought perturbation to the pull up circuit.

 

I have another question to this circuit.

 

In the VHDL sketch there are successive affectations: for insatance A<=B<=C to handle encoder signal and internal signals.

I understood this is to add registers, and prevent glitches but the process is a little bit hard to understand.

It was also explained in the encoder example of FPGA 4 fun, but it still difficult to me.

 

 

Well, enough for today!!

 

 

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This brings up a question I'd been meaning to ask. What is the purpose of those 82 Ohm resistors on the sync lines and how was that value arrived at? I thought they may just serve to provide some protection to the FPGA but 82R seems like a bit of an odd value.

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I assume that it is an attempt to match the impedance / voltage requirements of the VGA standard

 

- 0.7 V peak-to-peak

- 75 ohm double-terminated impedance (18.7 mA – 13 mW)
 
Ideal would be a 1.5V logic output driving through a 75 ohm resister...

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The RGB lines are 0.75V peak, but the sync inputs are 5V TTL logic. Most newer monitors will work just fine with 3.3V sync but I do have an old (ok ancient) Tatung CGA/EGA/VGA multisync that exhibits random horizontal jitter without 5V buffer on the Hsync line.

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