dawnpaul

MICRO BLAZE

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Woah! I didn't realize they added Microblaze MCS to the Coregen wizard of ISE. I had talked to the guy at Xilinx who was pushing for the simplified MCS version to be released, but didn't realize it made it that far! Wow, I need to put it on my task list to make a tutorial for this.

 

Jack.

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Yeah, I did play with it a bit and could synthesize it @ 120 MHz.  It's a 3-stage version of the Microblaze core (the high performance version use 5 stages) and is limited to 64 kB program space in bram (no sdram access).  It comes with a set of basic peripherals (uarts, timers, interrupt controller etc.) but it's easy to remove their peripherals and/or add our own if you so like.

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I looked at report for one of the systems I created, it had the UART and interrupt controller but no timers nor GPIO, and my own SPI controller.  It took up 342 slices on a Spartan-6 at 100 MHz.

 

BTW, Xilinx has a very detailed PDF-document about Microblaze_MCS. 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ds865_microblaze_mcs.pdf

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Ok, it's indeed small. Is there any quick doc showing the differences to the "normal" microblaze ?

 

I'm getting 328 slices for XTC in area optimization, 100MHz, only an UART. And I am still missing some parts of the design.

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