alex 21 Report post Posted August 29, 2013 Hey, what's up, the forum's been so quiet for the last week, are you all hibernating? If you are, here's a nice way to pass the time. Make a hot cuppa of your favorite beverage and sit back and enjoy this link to a nice half hour video I found of Colin, showing a step by step way of building a FIR filter. He is using Vivado for HLS (high level synthesys) to turn C code into VHDL/Verilog and then bring the output created by Vivado into the old school ISE environment to synthesize the FIR for a Spartan 3 FPGA. By being careful enough not to generate Virtex/Artix specific blocks, this technique can be used to turn almost any C code into functional synthesizable RTL for FPGAs not technically supported by Vivado. Pretty cool if you ask me. Share this post Link to post Share on other sites
Jack Gassett 0 Report post Posted September 3, 2013 Alex, Very interesting, thanks for the link. I'm going to give it a watch today and post to the blog for others to enjoy. Jack. Share this post Link to post Share on other sites
Jack Gassett 0 Report post Posted September 3, 2013 Oh! It's Colin O'Flynn, I had the pleasure of hanging out with him at Design West. Share this post Link to post Share on other sites
alex 21 Report post Posted September 30, 2013 Just a heads up, I saw in the latest issue of Circuit Cellar, in which Colin is a column contributor, that he has launched a new site at http://programmablelogicinpractice.com It's a freshly launched site and currently has next to no content, except for a couple of instructional videos "Inserting Logic Analyzer Cores" and "Advanced Features". I really enjoy Colin's presentation style and he covers very interesting topics, so I'll be keeping an eye on that site for fresh new content and hopefully it won't disappoint. Share this post Link to post Share on other sites
Jack Gassett 0 Report post Posted October 1, 2013 Great! Thank you for the heads up, I'm putting it on my feedly list. Jack. Share this post Link to post Share on other sites
