wildseyed

SID in Sketch, VHDL, or Both?

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I've been modifying the Retrocade Synth sketch to support two instances of the SID, like SID2SID, but I have not been able to locate any code on the VHDL side.  After downloading the Xylinx IDE, I opened the the XISE file, and it generated (is that the right word?) a project.  Looking in the results, I don't see anything relating to the SID, or the other synths.

 

I'm guessing that I'm only half way there at this point.  What am I missing?

 

Thanks.

 

 

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The VHDL SID code is located here. It should be possible to add two instances of the SID chip by opening this top level project and add another SID instance to an open wishbone slot. The official RetroCade variant is located here. But there is no Xilinx ISE project setup for that variant, you would have to use the makefile in the directory or make a new ISE project and add all of the files that are located in the *.prj file.

 

Jack.

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I noticed that there is a small diff between Voices 1-2, and Voice 3 in sid_6581.vhd

 

The snippet below is missing in voice 3.  Is this an oversight, or is it intentional?

 

signal Voice_2_Osc            : std_logic_vector(7 downto 0)    := (others => '0');
signal Voice_2_Env            : std_logic_vector(7 downto 0)    := (others => '0');
 

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