james1095

Arcade source

27 posts in this topic

Is there a collection of Papilio Arcade source that all properly synthesizes? I have a zip I downloaded a while back that says V1.0-4 but when I try to synthesize Pacman from that for the P1 500K I get a whole load of errors, mostly similar to this:

 

ERROR:NgdBuild:604 - logical block 'u_cpu/u0/mcode/Mmux_Set_BusA_To204' with
   type 'LUT6' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not
   supported in target 'spartan3e'.

 

I've tried synthesizing for the PPro and it does appear to succeed, however when I load the bitfile on the FPGA nothing happens. I was able to get MikeJ's original code ported to my Spartan3A starter kit and it synthesized without any problems and I can load the supplied bitstreams on my Papilio boards without issue but I haven't had any luck synthesizing these myself. Perhaps someone could point me to the latest working code? I've looked over the constraints file and it matches the pins listed on the Arcade Megawing page.

 

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The latest working source code is on Github. That zip file is probably an old copy before I made the changes to support the Papilio Pro. The Spartan 6 chips use a different synthesis engine that is much stricter, so in almost all cases there are some changes that need to be made before code written for Spartan 3E works on Spartan 6.

 

Can you send me a link to where you downloaded the V1.04 from?

 

Jack.

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Unfortunately it was a while ago so I don't recall the exact link, but I'm pretty sure I pulled it down from Github. It contains a project file "pacman_plx_lx9.xise" which does synthesize, it just doesn't work when I load it into the FPGA, despite me having copied good ROM images into the source.

 

Last night I did manage to port MikeJ's original code to the P1 500K with a Logicstart wing by using the pacman clocks source file from the Papilio folder and making a new constraints file and that works, now I can turn off the scan doubler and play with the micro joystick. I still haven't managed to get that to synthesize for the Spartan6 on the Pro. Is there an overview somewhere of the sort of changes that are needed? I'm finding Pacman to be a great platform for learning this stuff, it's complex enough to utilize lots of features, and everyone knows how Pacman is supposed to look so it's easy to tell when everything is working.

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Sorry, I don't have an overview, I usually tackle each issue as it comes up. In most cases I just google search the error and that points me in the right direction. They are usually minor syntax differences that need to be corrected because the new synthesis engine has a stricter interpretation of VHDL. Syntax that was ok for the old engine is not allowed by the new one. I've always found plenty of discussions about the errors on google that leads to a fix...

 

Jack.

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Cool, I'll give it another go. Seems like most of the errors I get from ISE are rather obtuse and a search finds much. I suppose this will get easier as I get a better grasp of VHDL.

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Please feel free to post any errors here and we can try to tackle them as a group.

 

Jack.

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I had some time to play with this some more tonight. I'm attempting to port the original code over to the LX9 on the PPro. It looks like I'm close, but I still get these errors:

 

ERROR:NgdBuild:604 - logical block 'u_dblsacn/u_ram_b' with type 'RAMB4_S8_S8'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'RAMB4_S8_S8' is not
   supported in target 'spartan6'.
ERROR:NgdBuild:604 - logical block 'u_dblsacn/u_ram_a' with type 'RAMB4_S8_S8'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'RAMB4_S8_S8' is not
   supported in target 'spartan6'.

 

 

This appears to be the block RAM used by the scan doubler. I'm pretty certain the author meant "u_doublescan" rather than "u_dblsacn" but I didn't change this when I ported the same code to the Spartan3 P1. Is this something anyone else has encountered?

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Spartan 6 does not support RAMB4 primitives and you have to change it to RAMB16. I have already ported all the games to PPro and so has Jack I believe. Are you sure you want to reinvent the wheel?

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Alex is right, that was another one of those differences between the Spartan 3E and Spartan 6. It was just a matter of changing the primitives to something that existed for both boards. I definitely remember going through all of this before. If you want to continue with trying to get this to port from Spartan 3E to Spartan 6 as a learning exercise I'd be happy to help guide you through it. But if you just want the source code that works on Spartan 6 I better get to the bottom of why you are getting the old code...

 

Jack.

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Cool, thanks, I'll give that a go. I'm doing this for two reasons, one as an exercise for myself starting with a known baseline, the same stumbling blocks are bound to occur when porting other Spartan3 designs. The other is to see if I can get it running on the Spartan6 without the corruption during the cutscene that occurs on the code that was already ported to the Papilio boards. You might recall from the other thread that I ported MikeJ's original code to the Spartan3 P1 and it works perfectly with no video corruption, as well as maintaining the ability to toggle the scan doubler.

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Well I changed these to RAMB16's and now I get some different errors:

 

ERROR:HDLCompiler:1314 - "C:\Xilinx\Projects\pacman_rel004_sp3e_lx9\source\pacman_dblscan.vhd" Line 147: Formal port/generic <rstb> is not declared in <ramb16_s9_s9>
ERROR:HDLCompiler:432 - "C:\Xilinx\Projects\pacman_rel004_sp3e_lx9\source\pacman_dblscan.vhd" Line 139: Formal <addra> has no actual or default value.
ERROR:HDLCompiler:1314 - "C:\Xilinx\Projects\pacman_rel004_sp3e_lx9\source\pacman_dblscan.vhd" Line 168: Formal port/generic <rstb> is not declared in <ramb16_s9_s9>
ERROR:HDLCompiler:432 - "C:\Xilinx\Projects\pacman_rel004_sp3e_lx9\source\pacman_dblscan.vhd" Line 160: Formal <addra> has no actual or default value.
ERROR:HDLCompiler:854 - "C:\Xilinx\Projects\pacman_rel004_sp3e_lx9\source\pacman_dblscan.vhd" Line 80: Unit <rtl> ignored due to previous errors.

 

 

While I have a lot of hardware and general electronics experience, I'm still a bit of a noob when it comes to VHDL. I'd appreciate a few pointers on this.

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Duuuuude...don't just take stabs in the dark read the doco :)

 

Go to xilinx.com and download both UG617 (Spartan 3) and UG615 (Spartan 6). You'll see in UG617 that rsta is replaced with ssra. You'll also see in UG615 that technically RAMB16_9_9 (and all it's other variants) is no longer supported in Spartan 6 and has been replaced with RAMB16BWER, however you can still get away with using it because XST is able to automagically perform a substitution at synthesis time.

 

Happy reading!

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Yes, the documentation will help sort this problem out.

 

Just in case, here is what I have:

 

SPOILER ALERT!!!!!!!!!!!!!!!!!!!!!!!!!!

	u_ram : RAMB16_S9_S9	generic map (		SIM_COLLISION_CHECK => "generate_x_only"	)	port map (		-- input		DOA               => open,		DIA               => rgb_in,		DOPA              => open,		DIPA              => "0",		ADDRA(10)         => '0',		ADDRA(9)          => bank_i,		ADDRA(8 downto 0) => hpos_i,		WEA               => '1',		ENA               => '1',		SSRA              => '0',		CLKA              => CLK,		-- output		DOB               => rgb_out,		DIB               => x"00",		DOPB              => open,		DIPB              => "0",		ADDRB(10)         => '0',		ADDRB(9)          => bank_o,		ADDRB(8 downto 0) => hpos_o,		WEB               => '0',		ENB               => '1',		SSRB              => '0',		CLKB              => CLK_X2	);

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Ok I got it working! I wasn't sure where those port names came from, but it seems they're hard coded in the software and not something that's part of the VHDL source.

 

There was an error in my constraints file causing the joystick directions to be all swapped around and I ran out of time this morning but I'll fix that later and see if the video corruption still happens. I'm currently using two separate RAM blocks in the scan doubler rather than the multiplexed setup in the Papilio code but I'll try consolidating that later.

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Ok this is now working perfectly on the LX9, so I've got Pacman running on both the Papilio One and the Pro with none of the graphics corruption, both with and without the scan doubler enabled! One last thing to do when I have a chance is swap in the other scan converter code and see if that brings back the corruption in the cutscene. For anyone interested, here's the current scan doubler code I'm using. The rest is MikeJ's original code with the Papilio pacman clocks file. Helps a lot to have those docs too, thanks!

 

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;

library UNISIM;
  use UNISIM.Vcomponents.all;

use work.pkg_pacman.all;

entity PACMAN_DBLSCAN is
  port (
    I_R               : in    std_logic_vector( 2 downto 0);
    I_G               : in    std_logic_vector( 2 downto 0);
    I_B               : in    std_logic_vector( 1 downto 0);
    I_HSYNC           : in    std_logic;
    I_VSYNC           : in    std_logic;
    --
    O_R               : out   std_logic_vector( 2 downto 0);
    O_G               : out   std_logic_vector( 2 downto 0);
    O_B               : out   std_logic_vector( 1 downto 0);
    O_HSYNC           : out   std_logic;
    O_VSYNC           : out   std_logic;
    --
    ENA_6             : in    std_logic;
    ENA_12            : in    std_logic;
    CLK               : in    std_logic
    );
end;

architecture RTL of PACMAN_DBLSCAN is
  signal ram_ena_12  : std_logic;
  signal ram_ena_6   : std_logic;
  --
  -- input timing
  --
  signal hsync_in_t1 : std_logic;
  signal vsync_in_t1 : std_logic;
  signal hpos_i      : std_logic_vector(8 downto 0) := (others => '0');    -- input capture postion
  signal ibank       : std_logic;
  signal we_a        : std_logic;
  signal we_b        : std_logic;
  signal rgb_in      : std_logic_vector(7 downto 0);
  --
  -- output timing
  --
  signal hpos_o      : std_logic_vector(8 downto 0) := (others => '0');
  signal ohs         : std_logic;
  signal ohs_t1      : std_logic;
  signal ovs         : std_logic;
  signal ovs_t1      : std_logic;
  signal obank       : std_logic;
  signal obank_t1    : std_logic;
  --
  signal vs_cnt      : std_logic_vector(2 downto 0);
  signal rgb_out_a   : std_logic_vector(7 downto 0);
  signal rgb_out_b   : std_logic_vector(7 downto 0);
begin

  p_input_timing : process
    variable rising_h : boolean;
    variable rising_v : boolean;
  begin
    wait until rising_edge (CLK);
    if (ENA_6 = '1') then
      hsync_in_t1 <= I_HSYNC;
      vsync_in_t1 <= I_VSYNC;

      rising_h := (I_HSYNC = '1') and (hsync_in_t1 = '0');
      rising_v := (I_VSYNC = '1') and (vsync_in_t1 = '0');

      if rising_v then
        ibank <= '0';
      elsif rising_h then
        ibank <= not ibank;
      end if;

      if rising_h then
        hpos_i <= (others => '0');
      else
        hpos_i <= hpos_i + "1";
      end if;
    end if;
  end process;

  we_a <=     ibank;
  we_b <= not ibank;
  rgb_in <= I_B & I_G & I_R;

  u_ram_a : RAMB16_S9_S9
    port map (
        -- input
        DOA               => open,
        DIA               => rgb_in,
        DOPA              => open,
        DIPA              => "0",
        ADDRA(10)         => '0',
        ADDRA(9)          => '0',
        ADDRA(8 downto 0) => hpos_i,
        WEA               => '1',
        ENA               => '1',
        SSRA              => '0',
        CLKA              => ENA_6,

        -- output
        DOB               => rgb_out_a,
        DIB               => x"00",
        DOPB              => open,
        DIPB              => "0",
        ADDRB(10)         => '0',
        ADDRB(9)          => '0',
        ADDRB(8 downto 0) => hpos_o,
        WEB               => '0',
        ENB               => '1',
        SSRB              => '0',
        CLKB              => ENA_12
    );

  u_ram_b : RAMB16_S9_S9
    port map (
        -- input
        DOA               => open,
        DIA               => rgb_in,
        DOPA              => open,
        DIPA              => "0",
        ADDRA(10)         => '0',
        ADDRA(9)          => '0',
        ADDRA(8 downto 0) => hpos_i,
        WEA               => '1',
        ENA               => '1',
        SSRA              => '0',
        CLKA              => ENA_6,

        -- output
        DOB               => rgb_out_b,
        DIB               => x"00",
        DOPB              => open,
        DIPB              => "0",
        ADDRB(10)         => '0',
        ADDRB(9)          => '0',
        ADDRB(8 downto 0) => hpos_o,
        WEB               => '0',
        ENB               => '1',
        SSRB              => '0',
        CLKB              => ENA_12
    );

  p_output_timing : process
    variable rising_h : boolean;
  begin
    wait until rising_edge (CLK);
    if  (ENA_12 = '1') then
      rising_h := ((ohs = '1') and (ohs_t1 = '0'));

      if rising_h or (hpos_o = "101111111") then
        hpos_o <= (others => '0');
      else
        hpos_o <= hpos_o + "1";
      end if;

      if (ovs = '1') and (ovs_t1 = '0') then -- rising_v
        obank <= '0';
        vs_cnt <= "000";
      elsif rising_h then
        obank <= not obank;
        if (vs_cnt(2) = '0') then
          vs_cnt <= vs_cnt + "1";
        end if;
      end if;

      ohs <= I_HSYNC; -- reg on clk_12
      ohs_t1 <= ohs;

      ovs <= I_VSYNC; -- reg on clk_12
      ovs_t1 <= ovs;
    end if;
  end process;

  p_op : process
  begin
    wait until rising_edge (CLK);
    if (ENA_12 = '1') then
      O_HSYNC <= '0';
      if (hpos_o < 32) then -- may need tweaking !
        O_HSYNC <= '1';
      end if;

      obank_t1 <= obank;
      if (obank_t1 = '1') then
        O_B <= rgb_out_b(7 downto 6);
        O_G <= rgb_out_b(5 downto 3);
        O_R <= rgb_out_b(2 downto 0);
      else
        O_B <= rgb_out_a(7 downto 6);
        O_G <= rgb_out_a(5 downto 3);
        O_R <= rgb_out_a(2 downto 0);
      end if;

      O_VSYNC <= not vs_cnt(2);
    end if;
  end process;

end architecture RTL;

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do you mind testing out `superglob` (german bootleg version), `pacman plus`, `jumpshot` and `shoot the bull` with your code when you get a chance? i am ~2000 km away from my papilio boards..   superglob shows the problem the best, followed by shoot the bull, then the others. 

 

note: superglob, jumpshot and shoot the bull arent playable atm due to controller mapping 

 

.bat files for building on the p500 are on here

https://github.com/FelixV/ROMGen_v3.01

along with a custom version of romgen. 

 

it would take a bit of tweaking the .bat files to work with the ppro ( filenames of the base bit and bmm )

 

the .rar is the same as bin_release directory. just extract, place roms in the right place and click the bats (after fixing filenames of bit/bmm)

 

regards,

felix

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I'll give it a try when I have a chance, my free time has been fairly limited lately but this stuff is fun. I have a P500 and a P-Pro so either one is easy enough to try. I assume the ROMs are easy to find? It's not really my code, for the P500k I simply used MikeJ's code un-altered along with the clocks file from the Papilio build and modified the constraints file so everything matched up. For the P-Pro I had to change the RAM types to work with the Spartan6 but that's the only change.

 

What's wrong with the controller mapping? Do those games use strange controls? Seems like that should be relatively easy to fix.

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yeah the roms are easy to find

 

jumpshot.zip

jumpshotp.zip

sprglb.zip

pacplus.zip

shootbul.zip

 

i think.  they are in the current mame sets.

 

shoot the bull requires a trackball and some buttons, (no clue on this one.. i have a usb/ps2 trackball *somewhere* but have no idea how to add support for it)

super glob requires 2 buttons (not enough buttons on the joystick)

jumpshot/jumpshotp require the start button to be the shoot/block button also. (should be easy here)

 

if you get bored, and are on windows, you can try my papilio arcade gamebase (requires install of the gamebase frontend)

[  http://www.gamebase64.com/gamebase.php ]

has all that stuff from arcade blaster, a few others not in there, and a manic miner someone posted on here in it (minus the roms)..

its on the same github linked acct from earlier.

 

i started on a papilio gamebase atari 2600 but ran into issues with the 2600 fpga code (seems a bit wonky

as some games work ok and some are just hosed.  it may be that i am using a different versoin of the IDE

than the one jack and company are using but i am not going to DL that huge thing again any time soon.  

i pretty much quit working on it due to that and a lack of time on my part, and interest from anyone else)

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PS/2 trackball is probably a good long term solution, but an easier way to get it working for now is probably interfacing to the quadrature encoders in a mouse or trackball directly as the original game would have done. I have a couple of Atari trackball assemblies in my parts stash as I've collected classic arcade machines for years, maybe I can try connecting one.

 

The others sound trivial, they could be wired up to the second joystick port on the arcade megawing.

 

Xilinx will send you a DVD with ISE on it for free if you sign up and request one.

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yeah but probably only the current one. i would need the prior one. 13.x i think.

 

yes wiring up jumpshot/jumpshotp/superglob is trivial but then you need a modified 2 button joystick to play :)

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I'm using ISE 14.2.

 

It's pretty simple to get a real arcade joystick and whatever buttons you want and mount them in a panel. It's usually a better result than using something like an old Atari joystick anyway.

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there's even a local shop for local people for Felix :P

http://www.arcadeshop.de/

tbf the same joysticks were used by many other systems and it's quite easy to find a suncom tac-2 in a good condition.

(or any of the spectravideo ones)

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yeah i know about joysticks. i have a converted x-arcade (the stock h/w is utter sh*t)

 

and a converted combat fighting stick. (kept joystick + top 2 buttons, got rid of crap sanwa knockoffs.

 

before:

 

post-29519-0-88672300-1370632359_thumb.j

 

after:

 

post-29519-0-19045500-1370632377_thumb.j

 

works top, for a €35 joystick (now)

 

going to pick up another one and convert it to NEO GEO pinout to use with my MAK supergun.

 

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there's even a local shop for local people for Felix :P

http://www.arcadeshop.de/

tbf the same joysticks were used by many other systems and it's quite easy to find a suncom tac-2 in a good condition.

(or any of the spectravideo ones)

 

thanks for that link vlait :) i hadn't seen that particular store :)

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In a pinch, just use whatever joystick you have, then mount a couple of buttons in some sort of panel and set it next to the joystick. I often use cardboard to lash up quick prototypes stuck together with packing tape. It's easy to cut with a knife, can be drilled with a punch or screwdriver, and it's reasonably sturdy. It worked when I was a kid and it still works. Once you have something you like, rebuild it out of a more durable material.

 

For trackball stuff, the encoders in a standard mechanical ball mouse are identical in function to those in a real arcade trackball. Supply power to the IR LEDs and take the signal off the phototransistors. Each axis will have a pair of phototransistors which will produce a set of quadrature encoded square waves that can be connected directly to the FPGA. Take care to use 3.3V though, many(most/all?) mice and trackballs originally ran everything at 5V.

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