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ZPUino on ppro

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.xise are just project files, while handy, they are not absolutely necessary. Just create a new project making sure to select the correct FPGA type and package and add all the source files. If a file is still missing it will be quite obvious in the hierarchy tree, just locate it an add it until the project synthesizes correctly. Basically you need to add to the project all the .vhd files, the ucf file for your particular board and make sure the correct file is selected as the top module.

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Maybe if you already know what you are doing... I don't think a single thing about that hierarchy tree is obvious. :P You add files and the most random things happen in that tree...

 

I've spent a couple hours attempting what you suggested without much luck. I had it able to synthesize for a bit, but it wouldn't translate so I added more .vhd files... then I was back to getting weird errors like "<undefined> is not declared". I don't know anywhere near enough about what's going on to create the .xise file this way...

 

... I just saw alvieboy's post after posting... I'll give a look through the .prj file before giving up. ;)

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Thanks for the tip :-) Unfortunately, I have the following error:

 

ERROR:NgdBuild:604 - logical block 'slot14/sid/fblk.filters' with type   'sid_filters' could not be resolved. A pin name misspelling can cause this, a   missing edif or ngc file, case mismatch between the block name and the edif   or ngc file name, or the misspelling of a type name. Symbol 'sid_filters' is   not supported in target 'spartan6'.

Ideas?

 

UPDATE: Nevermind... Missing files.

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Actually, now that I was able to synthesize and bitstream it to the FPGA, the ZPUino IDE gives me a verification error whenever trying to upload anything. I don't have my Papilio Pro here, but once I arrive home, I'll post the message.

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Here's the error:

 

 

Binary sketch size: 892 bytes (of a 12160 byte maximum)Board: Unknown board @ 96000000 Hz (0xa4041700)Verification failed at 0x00060000!00 00 10 00 31 0a fa de a4 04 17 00 0b 0b 0b a0 94 04 00 00 0b 0b 0b 0b 88 08 0b 0b 0b a0 90 2d 0b 0b 0b 0b 88 0c 04 00 00 00 00 00 02 d0 05 0d 00 40 09 00 00 00 00 00 80 00 00 00 00 14 04 00 01 02 88 00 00 20 00 25 13 00 00 10 00 00 00 00 20 00 00 08 01 00 00 01 00 10 20 90 0c 00 00 01 08 04 00 00 40 00 00 00 00 80 10 20 40 00 00 00 88 00 00 00 00 00 00 00 00 80 00 00 00 00 24 00 00 00 00 00 00 08 00 00 04 40 00 80 01 01 02 0a 00 00 10 09 04 01 00 00 01 00 02 20 00 00 00 00 00 10 03 00 00 02 00 00 00 00 00 01 00 01 04 a0 00 00 00 00 04 00 00 80 40 51 02 98 00 01 00 00 00 00 00 02 00 00 40 08 00 00 a8 04 08 00 00 04 00 00 80 00 00 04 04 00 00 01 80 18 00 20 80 00 00 80 04 00 50 00 00 00 00 00 80 00 00 01 00 02 21 a0 40 00 00 10 01 00 00 00 00 00 00 50 08 00 00 df 58 e2 31 0a fa de a4 04 17 00 0b 0b 0b a1 df 04 00 00 0b 0b 0b 0b 88 08 0b 0b 0b a0 df 2d 0b 0b 0b 0b 88 0c 04 00 00 00 00 00 02 f8 05 0d 80 52 8d 51 a0 e0 2d 02 88 05 0d 04 02 f4 05 0d 81 52 8d 51 a0 f4 2d af d7 c2 80 70 52 53 a1 f0 2d 80 52 8d 51 a0 f4 2d 72 51 a1 f0 2d 02 8c 05 0d 04 04 04 70 80 c8 80 80 90 52 a0 fc 04 70 80 c8 80 80 a0 52 a0 fc 04 70 81 90 0a 52 a0 fc 04 72 0a 83 2b 0a fc 06 72 05 70 08 81 75 9f 06 2b 76 88 38 09 06 71 0c 50 51 04 07 71 0c 50 51 04 71 70 33 86 38 72 31 88 0c 04 81 05 a1 9d 04 a8 08 04 02 f8 05 0d a6 f8 52 71 a6 fc 2e 93 38 71 70 84 05 53 08 51 70 2d 71 a6 fc 2e 09 81 06 ef 38 02 88 05 0d 04 04 a0 a8 2d a0 b8 2d a0 b8 2d a1 d6 04 02 f8 05 0d a1 ae 2d 80 52 80 51 a1 d3 2d a1 ed 04 02 f4 05 0d 80 cc 80 80 8c 70 08 76 Programming completed WITH ERRORS in 0.83 seconds.

According to this topic http://forum.gadgetfactory.net/index.php?/topic/1588-how-to-program-the-arduino-sketch-for-zpuino-to-the-spi-flash/page-2, I should replace the programmer .exe file in the tools folder... But my tools folder doesn't have any subfolder named zpu, nor any binary inside.

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It must have, you're looking in the wrong place.

There exist two tools folders. Care to search on your installation for the zpuinoprogrammer.exe ?

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Oh yeah, now I see it... :-) It seems able to upload sketches now, great!

 

Two things: (1) Does anyone know what is the "arduino-level" port of the internal led? (P112?)

 

And (2) when uploading the "ASCII Table" sketch, serial monitor (or putty) only receives the following:

 

"ASCII Table ~ Character Map

!, dec:"
 
... and it stops. Resetting the board leads to the same result. Thoughts?

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try using the FPGA_LED_PIN macro for the led.

Regarding the other issue: since the programmer might have erased parts of the bitfile: can you try programming the bitfile again and then the sketch?

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Hey Alvie,

 

Thx for all the help so far :-) The FPGA_LED_PIN macro worked like a charm, and the led keeps blinking in the typical 'hello world - blink led' sketch, so the ZPU seems to be running.

 

However, the communications over the Serial Port remains problematic. The ASCII Table sketch stops at the same point, and it is related to the Serial.print(thisByte); Commenting this line out seems to fix. If I try different values for thisByte, then, for some completely obscure reason for me, anything below 80 trashes the serial and eventually freezes. o.O

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I have bumped into some problems getting the ZPUino to compile correctly. I also posted an ISE project file in hopes that once these issues are overcome, it can make it easier for others to start using this. See files posted here. 

 

http://code.google.com/p/daecu/source/browse/#svn%2Fmisc%2FFPGA%2FZPUino-HDL_project

 

Currently I get an error message as noted below. 

 

 

Annotating constraints to design from ucf file
"/home/jharvey/Desktop/papilio_SOC-master/gadgetfactory/ZPUino-HDL/zpu/hdl/zpuin
o/boards/papilio-pro/S6LX9/papilio_pro.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
 
Done...
 
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'bootmux' with type 'wbbootloadermux' could
   not be resolved. A pin name misspelling can cause this, a missing edif or ngc
   file, case mismatch between the block name and the edif or ngc file name, or
   the misspelling of a type name. Symbol 'wbbootloadermux' is not supported in
   target 'spartan6'.
ERROR:NgdBuild:604 - logical block 'zpuino/core' with type
   'zpu_core_extreme_icache' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'zpu_core_extreme_icache' is not supported in target 'spartan6'.
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
  Number of errors:     2
  Number of warnings:   0
 
Total REAL time to NGDBUILD completion:  14 sec
Total CPU time to NGDBUILD completion:   11 sec
 
One or more errors were found during NGDBUILD.  No NGD file will be written.
 
Writing NGDBUILD log file "papilio_pro_top.bld"...
 
Process "Translate" failed

 

 

I have been googling this and fumbling around, but haven't figured it out yet. Any suggestions on what to look for or how to correct this such that it compiles?

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I tried https://github.com/alvieboy/ZPUino-HDL.git switched to the lsu branch, then I used the two files (sid_filters.vhd and sid_coeffs.vhd) which I found in Jack's repo. I got the same results as posted above. I also found those couple missing .vhd files here http://netsid-papilio.googlecode.com/svn/trunk/ and still no dice. 

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I'm using ISE and trying to make a project based on the project file. I don't know how to use the makefile, I assume it will require specific compiler tools installed, which I probably do not have installed. 

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Ok, you'll have to add the missing files then to the ISE project.

 

"zpu_core_extreme_icache.vhd" and "wbbootloadermux.vhd" should be present in "hdl/zpuino".

 

https://github.com/alvieboy/ZPUino-HDL/blob/lsu/zpu/hdl/zpuino/zpu_core_extreme_icache.vhd

https://github.com/alvieboy/ZPUino-HDL/blob/lsu/zpu/hdl/zpuino/wbbootloadermux.vhd

 

Others might be missing. Usually the filename and the entity name are the same.

 

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