MartyMacGyver

Papilio Pro + LogicStart MegaWing - n00b how-to with some questions as well

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(This includes observations and details that may be of use to other new users and those new to the Pro, as well as my own questions to follow.)

 

What I'm using:

Notes:

Install the Papilio Loader, the Xilinx WebPack software, and the Xilinx Device Pack. Create the license for the free features of the ISE Design Suite and import that license (which you'll receive via email) to the ISE Design Suite.

 
Open the ISE Design Suite and create a new HDL project with Spartan-6 settings appropriate to the Papilio Pro (Note that "Enable Message Filtering" is optional but useful):

 

post-36544-0-32119800-1361059789_thumb.j

 

(At this point I'm mostly following the Intro to Spartan FPGA book with some important changes.)

Add a new source VHDL module. Rather than using the wizard, I pasted in the source for this entity directly from the book (be sure to edit out any cruft if your copy spanned a page-break). Note that the entity name doesn't need to match the module name.

 

Add an Implementation Constraints file (I called mine constraints.ucf). This was a little more tricky, since the pins in the book are for the Papilio One 500K, not the Pro.

 

Retrieve the BPM7003-Papilio-Pro-LogicStart-MegaWing-general.ucf file and use it to find the appropriate pin mappings for the Pro (if you cut-and-paste these from the UCF, be sure to rename them accordingly!) This is what I used:

NET SWITCH_0  LOC="P114" | IOSTANDARD=LVTTL; # C0NET SWITCH_1  LOC="P115" | IOSTANDARD=LVTTL; # C1NET LED_0     LOC="P123" | IOSTANDARD=LVTTL; # C8NET LED_1     LOC="P124" | IOSTANDARD=LVTTL; # C9

Select the VHD file and you'll see the option in the pane below to "Generate Programming File". Run it. You shouldn't get any warnings or errors for this example.

 

Plug in the Papilio Pro (with the LogicStart wing attached). Ensure the drivers load (it may take a short bit the first time you use it).

 

Start the Loader and select the .bit file you just created in your project area (leave the .bmm and .hex file entries blank). Be sure "SPI Flash" is selected below "Write to".

post-36544-0-51515600-1361062761_thumb.j

 

Select "Do Selected Operations" and wait for the programming process to complete successfully (there's troubleshooting info in the book and on the forums here).

 

Try it out! The switches enabled by this module happen to control the LEDs above them. Change things! Swap switch_0 and switch_1 in the architecture section of the design, rebuild and upload again - now the switches control the opposite LEDs.

 

Hopefully you find this quick-start useful! I have some questions which I'll add in the first comment below.

post-36544-0-32119800-1361059789_thumb.j

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The one big question I have is, does one ever use the entire constraints file? If I do so I get several errors, particularly about PULLUP ("Constraint <PULLUP;> ... not found"), CLK ("NET "CLK" not found") and others.

 

  • For the missing NETS, is it simply because those extra constraints are unused? I thought perhaps they'd simply be ignored but evidently not.
  • Isn't PULLUP a standard keyword of some sort? If not, where would you normally define it?
    Edit: It appears the PULLUP complaint is part of the error cascade, and it seems to be accepted in the focused example above)

Given BPM7003-Papilio-Pro-LogicStart-MegaWing-general.ucf, can one use it correctly as-is, or is it always chopped up in use?

 

Edit: Another question: When creating/configuring a Papilio Pro project, is a speed of -3 or -2 more appropriate? I just noticed -2 mentioned on the pinout guide page though I've used the default of -3 until now.

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Hi,

 

You need to remove all unused "references" in the UCF file. Each design should have it's own UCF and tailored for the specific design.

If you leave unused references there, it's just like having an electronic schematic with extra components which are not connected to anything.

 

Regarding PPro speed, it's indeed "-2".

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You need to remove all unused "references" in the UCF file. Each design should have it's own UCF and tailored for the specific design.

If you leave unused references there, it's just like having an electronic schematic with extra components which are not connected to anything.

 

FYI, in the process of investigating something else I stumbled upon this informative thread... evidently you can also use a setting to ignore unused constraints (which would save fiddling with the UCF for a component like the LogicStart).

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