RonCK

Custom Cores with Xilinx ISE 14.4?

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Jack,

 

    I'm using your v1.6 Aurduino Soft Core with the template for a custom user core enabled.  I have port A fully assigned and driven freely by the HDL code in the custom core.  I can download the synthesized .bit file directly from ISE and I see the port A pins responding.  I've used the copy-to-custom.cmd script to copy the bit file over to the Arduino directory.  I can then compile essentially any code and see in the verbose output that the ROM file has been updated in the Xilinx directory.  I can simulate this and see the port A pins do what I expect them to.  But, if I download the output .bit from the Arduino compiler as soon as setup() completes, the core loses control of the port A pins.  Any idea why this would be the case?   I started with the cImplPORTA generate constant defined as FALSE and the cImplpapilio_core_template as TRUE and have tried numerous combinations to where I now have completely commented out everything in the top level hdl file related to port A and the user core and have greatly simplified my port A code and put it directly in the top module (and changed the porta pin definitions to be out only) and have seen no change in the behavior with HDL + Arduino code.  Any help would be appreciated.  (current top level hdl code attached)

 

best regards,

Ron

Papilio_AVR8.vhd

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Hello,

 

I believe that for a Papilio One with Spartan 3E FPGA, you need to use Webpack ISE 14.3 as Xilinx has removed support for the Spartan 3E IP cores from ISE 14.4.  It suspect this is probably the root of your problem.

 

The ISE 14.3 download is still available from Xilinx.

 

- Xark

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Xark,

 

   I suppose that is possible.  I was unable to use the core builder until I added this environment variable:  XIL_CG_LOAD_ALL_FAMILIES = TRUE.  Then the IP cores were usable.  I have continued my debug and now I seem to be able to run HDL code in the chip as long as I have no C loaded into the Arduino and I can run C, but doing so seems to shut off my functionality to the port A pins.  I'm guessing at this point that there is something buried in the Arduino C libraries that is causing the problem but I have no idea what to look for.

 

Best regards,

Ron

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A similar thing happened to me. Following Mikes Hamster tutorial book, and onto the chapter about generating RAM & ROM,  I couldn't gain access to any of the cores in the core generator for my Papilio 500K. I mean none.

After a bit of delving I found a post on this site about the problem. 

I Uninstalled 14.4 and installed 14.3.

A bit of a pain but the cores are all there now. :)

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Hello,

 

OK, I revisited the 14.3 vs 14.4 ISE issue today.  I was previously unaware of the XIL_CG_LOAD_ALL_FAMILIES workaround however while reading up on that, I found that Xilinx now has a proper "device pack" upgrade available here: http://www.xilinx.com/support/download/index.htm

 

After installing the update, I no longer have problems any problems using 14.4 with Spartan 3E (Yay).

 

Now I am not so sure this is related to your problem, but you may want to install the "device pack" anyways (unlikely to hurt).

 

- Xark

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Xark,

 

   Thank you, that helped a great deal.  Now the output file from ISE works. I am apparently fighting two problems though as the Arduino generated uploads still don't work.  If I synthesize again with the updated ROM image the ISE generated file works.  I compared the papilio_avr8.bit != the out.bit file in the Arduino build directory.  Are you using Jack's Arduino IDE0018g?

 

Best regards,

Ron

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Victory! Well, mostly.  I updated the Arduino software and then had to make a change to the script file to update the custom.bit directory as they moved.  At least now when I hit upload in Arduino both my HDL and my C code are working.

 

Best regards,

Ron

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