Jack Gassett

Papilio SOC (Build System on Chip with Schematic Editor!)

57 posts in this topic

Now that I've had a chance to play with some of the basic features, I can say this is really cool and I like it allot. I'd say it's at least as cool as it looks in the sneak peek video. Also I'm looking forward to building a module, and playing with those symbols that are already created. 

 

Are there any suggested tutorials or videos about how to use ISE. I'm seeing what I can find via google searching. If I find some that look like they are handy references, I'll be sure to post about them. 

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I'm almost ready to get a Papilio board. I have a couple questions before I finalize what I decide to get. The first question, can I reuse my Logic Sniffer? I foresee it being problematic as it's behind a different 232 chip. I'm assuming it will be reasonably hard to use the sniffer, if it can be used at all. So my next question would be, at this time, am I better with the pro or the 500k, or other? I think the 500k is the most popular and most tested, while I've seen some notes that things need to be moved over to the pro before they can be used. I suspect both can easily fulfill what I'm looking to do, as most of what I'm doing is very simple compared to what I've seen done with an FPGA. What I'm looking for is basically an Arduino processor block, with some dedicated hardware for internal combustion specific IO. Below is a high level overview of my goals and what I'm looking to do with this FPGA. 

I'm looking to use this as a building block of an engine control / diagnostics device. The first thing I want to do is to simulate a pulse train that's very similar to what is found on an engine. I think this should be fairly easy. I'm picturing taking a piece of RAM or ROM, then using a counter connected to a clock and a comparator that resets every blah often. Such that a number is incremented and reset continuously. The incremental number can be routed to the ROM or RAM memory block address such that every blah seconds, a new bit is put out the memory block. Then to simulate a rotary encoder like those found on an engine, you simply draw the pulse train in the RAM/ROM block and clock it out with a variable clock. For example, a 36-1 signal wheel (that's 35 senses teeth and one gap for 35 pulses and one skipped pulse) The timer could be set to 72, such that the memory block spits out up to 72 different bits from memory. Then the memory would have every other bit set, with one exception where three bits would be contiguous 0's. The results should look something like the below. To change the rotational speed of the rotary encoder, you simply change the clock that's connected to the incremental number.

361trigger.jpg

Some longer term goals would be to increase the memory to at least 3600 for a .1 degree resolution, and eventually decode this signal into a rotational angle measurement, that's reported to a register somewhere.

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I'm looking to use this as a building block of an engine control / diagnostics device. The first thing I want to do is to simulate a pulse train that's very similar to what is found on an engine. I think this should be fairly easy. 

That will be pretty easy to do in straight VHDL  :) 

 

Just set up a 72 bit shift register with "AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8" and then once in a while (e.g. every 1,000 ticks of the 32MHz clock) roll the shift register:

 

process(clk)

  if rising_edge(clk)

     if counter = 1000 then 

       shift_reg <= shift_reg(0) & shift_reg(shiftreg'high downto 1);

       counter <= 0;

    else

       counter <= counter + 1;

    end if;

 end if;

 

Dynamically setting the "1000" to something else can be used to change the speed of the pulse train, so that is what needs to be set by the soft processor's program (if one is needed at all for this application!)

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I have a fairly basic outline of a ZPUino, and I'm following the same basic steps noted in the "Build LogicStart with Papilio DrawDuino System on Chip Library" video. When I do the "view HDL functional template" I get the below error messages. I started with the V0.1 zip noted above. It would seem there is some kind of configuration bits that I need to set, but I don't know what it might be. 

 

ERROR: Failed to load symbols for /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip-Papilio-SOC-V0.1/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch no netlist will be generated

ERROR: Could not find symbol "zpuino_empty_device"

ERROR: Could not find symbol "ZPUino"

ERROR: Could not find symbol "zpuino_uart"

 

About the VHDL and shift register, I'm reasonably ignorant about FPGA. I'm reasonably sure that if else statements aren't VHDL code, and I'm a bit ignorant about how to setup the shift register. I've looked at the shift register block in the SOC, but your notes didn't jump out to me about how to set the AAAAAAAAAAAAAAAA8 thing. I'm a NOOB who's brave enough to get into trouble, so I'm fumbling around, trying to learn. 

 

Some long term goals are to change the speed via serial stream, and to send the speed via serial stream. I also have some example programs that could be ported to the ZPINO that will interface a bunch of PC software with the serial stream. So my goal would be to use the ZPUINO to update the shift registers, and eventually read the decoded registers. 

 

I also wonder should this be a different thread? Or at least should the parts about the rotary encoder stuff be a different thread?

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About the VHDL and shift register, I'm reasonably ignorant about FPGA. I'm reasonably sure that if else statements aren't VHDL code, and I'm a bit ignorant about how to setup the shift register. I've looked at the shift register block in the SOC, but your notes didn't jump out to me about how to set the AAAAAAAAAAAAAAAA8 thing. I'm a NOOB who's brave enough to get into trouble, so I'm fumbling around, trying to learn. 

 

What hamster wrote above is actually functioning VHDL code, contrary to your belief if/else statements actually make up a very important part of all register transfer level VHDL code.

 

The bit that is missing from hamster's example is the signal definitions with types for the signals named in the process.

 

As for setting a shift register the VHDL code to accomplish this using the above naming would be:

 

signal shift_reg : std_logic_vector(71 downto 0) := X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8";

 

This creates a signal (the name vhdl has for what would normally be called a variable in software, however it has somewhat different connotations since we are writing hardware) which is a 72 element array of std_logic which is then initialized to "AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8" 

 

A custom VHDL wishbone core could be written that can then be interfaced to the ZPUino in order to give software control via a number of registers and feedback by the same.

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Ooop, it would appear my VHDL ignorance is showing through :) That's one reason why I was trying to get the view HDL thing working. I'm currently fumbling with often incomplete examples, the view HDL should be fairly complete, and should help fill in many gaps for me as I don't currently know what to expect in the overall picture. Once I have played with some complete examples, I'll have a better gut feel for when I'm looking a sub sections like Hamster posted. 

 

I still don't know why or how to fix the error thing. 

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I'm almost ready to get a Papilio board. I have a couple questions before I finalize what I decide to get. The first question, can I reuse my Logic Sniffer? I foresee it being problematic as it's behind a different 232 chip. I'm assuming it will be reasonably hard to use the sniffer, if it can be used at all. So my next question would be, at this time, am I better with the pro or the 500k, or other? I think the 500k is the most popular and most tested, while I've seen some notes that things need to be moved over to the pro before they can be used. I suspect both can easily fulfill what I'm looking to do, as most of what I'm doing is very simple compared to what I've seen done with an FPGA. What I'm looking for is basically an Arduino processor block, with some dedicated hardware for internal combustion specific IO. Below is a high level overview of my goals and what I'm looking to do with this FPGA. 

The Logic Sniffer is not suitable for FPGA designs, it has tiny 50mA voltage regulators and the PIC chip makes it difficult to reprogram. It was conceived from the beginning as a single purpose board, so I don't recommend wasting time with it for this purpose.

 

For your purposes, whether the Pro or the 500K is better. The 500K is better supported because it's been around longer, but the Pro is so much nicer that I think that will change. For your case though, I think it comes down to how much code space you will need with the ZPUino. The Papilio Pro has 8MB (64Mb) of code space available! That is more then you will probably ever need. The Papilio One 500K runs out of code space around 24KB if I remember correctly... The other consideration is that I am starting out the Papilio SOC using the 500K right now, I haven't even started trying to get it to work on the PPro yet.

 

I'm looking to use this as a building block of an engine control / diagnostics device. The first thing I want to do is to simulate a pulse train that's very similar to what is found on an engine. I think this should be fairly easy. I'm picturing taking a piece of RAM or ROM, then using a counter connected to a clock and a comparator that resets every blah often. Such that a number is incremented and reset continuously. The incremental number can be routed to the ROM or RAM memory block address such that every blah seconds, a new bit is put out the memory block. Then to simulate a rotary encoder like those found on an engine, you simply draw the pulse train in the RAM/ROM block and clock it out with a variable clock. For example, a 36-1 signal wheel (that's 35 senses teeth and one gap for 35 pulses and one skipped pulse) The timer could be set to 72, such that the memory block spits out up to 72 different bits from memory. Then the memory would have every other bit set, with one exception where three bits would be contiguous 0's. The results should look something like the below. To change the rotational speed of the rotary encoder, you simply change the clock that's connected to the incremental number.

361trigger.jpg

Some longer term goals would be to increase the memory to at least 3600 for a .1 degree resolution, and eventually decode this signal into a rotational angle measurement, that's reported to a register somewhere.

 

 

Sounds really cool. :)

 

Jack.

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I have a fairly basic outline of a ZPUino, and I'm following the same basic steps noted in the "Build LogicStart with Papilio DrawDuino System on Chip Library" video. When I do the "view HDL functional template" I get the below error messages. I started with the V0.1 zip noted above. It would seem there is some kind of configuration bits that I need to set, but I don't know what it might be. 
 
ERROR: Failed to load symbols for /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip-Papilio-SOC-V0.1/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch no netlist will be generated
ERROR: Could not find symbol "zpuino_empty_device"
ERROR: Could not find symbol "ZPUino"
ERROR: Could not find symbol "zpuino_uart"
 
About the VHDL and shift register, I'm reasonably ignorant about FPGA. I'm reasonably sure that if else statements aren't VHDL code, and I'm a bit ignorant about how to setup the shift register. I've looked at the shift register block in the SOC, but your notes didn't jump out to me about how to set the AAAAAAAAAAAAAAAA8 thing. I'm a NOOB who's brave enough to get into trouble, so I'm fumbling around, trying to learn. 
 
Some long term goals are to change the speed via serial stream, and to send the speed via serial stream. I also have some example programs that could be ported to the ZPINO that will interface a bunch of PC software with the serial stream. So my goal would be to use the ZPUINO to update the shift registers, and eventually read the decoded registers. 
 
I also wonder should this be a different thread? Or at least should the parts about the rotary encoder stuff be a different thread?

 

I think you still ended up with the wrong download... I posted a zip file that had everything in that first thread I posted earlier, here is a direct link to the zip file.

 

Jack.

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I don't know what to do with those files. They are mostly .cpp and .h the .ino file looks like the master file perhaps it's a sketch. The missing files were .vhd. Do I need to copy those files into the file structure I have downloaded via github? Do I need to make those files compile some how? Perhaps I grabbed the incorrect github. I'm drawing blanks here. 

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I'm not in a huge rush, and I suspect long term I'll need the larger code space, so I'll get the pro. How hard is it to change the project over, I don't see a way to change it from looking over the pull downs in ISE, so I suspect a new project will need to be created, then copy over most of the various configuration files and such.

 

I think that for the short term I'll focus on making an analog input and output wing. I had once planned for an Arduino shield, and I created a shield that could connect to most engines. I posted it here. http://daecu.googlecode.com/svn/Hardware/trunk/KICAD_Project_Arduino_AN_IO/arduino_injector_analog_schematic.pdf PCB layout and KICAD files also found there. I posted about the analog protection and filter here http://code.google.com/p/daecu/wiki/AN_and_DIGI_Protection as well I posted about the injector drive circuit here http://code.google.com/p/daecu/wiki/Injector_driver_theory However a key issue I have with the FPGA, is it's lack of AN inputs. 

 

I think I'll first converting the Eagle wing into a KICAD wing. Then I'll change that wing such that the FPGA can have an analog input option. I guess I should inquire, if I made an analog input board, what might people suggest for features? For engine control you typically only need like 1kHz and 8 bit would probably be good enough, but why not aim for something more. I would probably aim for features similar to an Arduino shield, such that if this board is installed, it can make a near exact match to an Arduino shield. This would allow my engine interface shield to be used as is. I could see this analog board being used as a kind of play recorder, something that would allow me to record data from an existing engine, then play it back such that software folks can analyze and tune an engine with out being connected to it. 

 

This approach works well for me, as I'm far weaker with software than hardware. While I wait for the pro, and start this board layout, it will give me some time to learn the extreme basics of VHDL. So does anyone have a wish or desire when it comes to analog inputs? Perhaps those the build and sell boards might want to steer in a particular direction. I don't plan to MFG the board, but I can design it, and I'd be happy to buy it if someone were to MFG it. 

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The Retrocade and LogicStart Megawings each provide analog inputs by means of an SPI ADC chip, this is going to be the easiest way for low sample rate inputs such as yours.

If you do not require high accuracy its possible to hack a SigmaDelta ADC with an FPGA input buffer as the 1bit ADC element however this is probably not the best way to do anything.

For high sample rate applications I believe SERDES ADCs are available and could probably be used with the papilio.

 

Take a look at the various megawings available for the commonly used ADC cicuits.

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Perfect, I just got the Retrocade bundled with the Pro. My only concerns are that the inputs and outputs might not be rugged enough for the noisy environment around engines, but that's easily solved with some fairly easy to make op-amp buffers. That 1nF and resistor for the ADC might be good to put in on an op-amp buffer card as well,

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I don't know what to do with those files. They are mostly .cpp and .h the .ino file looks like the master file perhaps it's a sketch. The missing files were .vhd. Do I need to copy those files into the file structure I have downloaded via github? Do I need to make those files compile some how? Perhaps I grabbed the incorrect github. I'm drawing blanks here. 

 

Doh! Sorry, I thought I had packaged up the HDL source code in that zip file too. You are right it is only the ZPUino sketch, not what you need. The weird thing is that other people have run the project without missing those symbol files... This should be the GitHub you need:

https://github.com/GadgetFactory/Papilio_System_On_Chip

 

Is that what you are working from?

 

If so then have you added the symbol library to the project?

 

Jack.

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I set the symbols per the SOC sneak peek video which allowed the schematic to show correctly. Before adding the symbols the schematic failed. Also those files don't appear under the stuff I've downloaded, so i don't think the issue is with a missing link, I think the problem is that I don't have those files.

 

I have downloaded the git copy, and zip copy, and placed them in different folders. I can change between the two projects by simply opening the other project. 

 

Perhaps these files are included in a different file that others happened to use. I looked in the LogicStart files, but only found the .ucf. Could they be under a different project like the arcade? 

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I feel sheep-ish right now. I figured out the problem with github and finding Papilio_Default.vhd. It appears I was looking for the .vhd files under the zip project not the github project. Sorry for buggering that and thanks for the help/support. 

 

When setting the symbol location, where should the schematic draw path point? I set it to the same folder as the xlinx.libs, as that has lots of space to work with, and it defaulted to that folder as I had just set the symbol location. However it appears I still have a symbol problem when using the github copy of the project. I'm assuming it wants some place where there is lots of space. I currently get this error message, when I try to view functional HDL model. 

 

 

Command Line: sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl Papilio_SOC_Base.vhf -w /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip-master/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch
ERROR: Failed to load symbols for /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip-master/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch no netlist will be generated
ERROR: Could not find symbol "zpuino_empty_device"
ERROR: Could not find symbol "ZPUino"
ERROR: Could not find symbol "Papilio_Default"
 
When I set the symbols, and I'm at the last dialog of setting the symbols, I get a note that the libs have to be saved to the same folder as the schematic symbols. Perhaps that's the problem, and I don't have the schematic draw path correct. I'm still fumbling through this. 

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hello jack , i have the same problem , when i download your porgramm and launch it, i have the same error message that "kb1gtt"

 

i thinks that in your zip , there is not all files ;(

 

thanks

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Hello Jack,

 

I've been absorbing the great FPGA book, and now I'm starting to look at the SOC thing again, hopefully with less ignorant eyes :)

 

I just downloaded the above zip file, and extracted to a folder titled Papilio_System_On_Chip_jack I moved the symbols location to this new folder, however it still appears I don't have the correct ZPUino symbols. When I open Papilio_SOC_Base.xise then click the green arrow, I get this in the console. 

 


Running sch2hdl...

Command Line: sch2hdl -batch /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip_jack/example_SOCs/Papilio_SOC_Base/sch2HdlBatchFile
Release 14.4 - sch2hdl P.49d (lin64)
Copyright © 1995-2012 Xilinx, Inc.  All rights reserved.
ERROR: Failed to load symbols for /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip_jack/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch no netlist will be generated
ERROR: Could not find symbol "zpuino_empty_device"
ERROR: Could not find symbol "ZPUino"
ERROR: Could not find symbol "Papilio_Default"
ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'can't read "iFileType": no such variable'.
Tcl_ErrnoId: unknown error
Tcl_ErrnoMsg: Success
_cmd: ::xilinx::Dpm::dpm_chTransformExecuteNoClean dpm_ecsConvertSchematics $piThisInterface
errorInfo: can't read "iFileType": no such variable
    while executing
"if { $iFileType eq "UNKNOWN" } {
                continue ; # unknown is just ignored, its probably .txt
              }"
    ("foreach" body line 3)
    invoked from within
"foreach sItem $lOutputFileList {
            if { ![dpm_parseOutputFile $sItem $iDesign sFile iFileType fileOrigination] } {
              if { $iFile..."
    (procedure "dpm_chTransformOutput" line 15)
    invoked from within
"dpm_chTransformOutput $piTranInst $lOutputFileList"
    (procedure "dpm_ecsConvertSchematics" line 132)
    invoked from within
"$sCmd $iTransformInstance $sCmdArgs"
    (procedure "dpm_chTransformExecuteEngine" line 100)
    invoked from within
"dpm_chTransformExecuteEngine $sFlowProc $iInterface $bRunTransformWithEmptyInputSet false "
    (procedure "::xilinx::Dpm::dpm_chTransformExecuteNoClean" line 3)
    invoked from within
"::xilinx::Dpm::dpm_chTransformExecuteNoClean dpm_ecsConvertSchematics $piThisInterface"

 

Also when I open the schematic, I get the below. ZPUino_broken.png

 

Perhaps you have your symbols pointing to a different directly than what I have it pointed to. Mine are point to

 

/home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip_jack/xilinx_libs/Papilio_SOC.lib

 

I extracted the zip file to /home/jharvey/Desktop/papilio_SOC-master/Papilio_System_On_Chip_jack/

 

I get very similar with LogicStart.xise which is the other ise project that is included in the zip file. 

 

I found a project under ./soft_processors/ZPUino-HDL/zpu/hdl/zpuino/boards/papilio_one/ that came close compiling. 

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I wonder if there is an issue with case sensitivity in the paths? Windows doesn't care about case but linux does, maybe that is causing a problem?

 

Jack.

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The symbol schematic shows a graphic, however it appears to not be the correct graphic as it has all that red, and there is an unused port hanging off the end where you appear to have added some stuff to the symbol. I used the "browse" button to get the path setup in the lib manager. I have also looked into the noted sch2HdlBatchFile batch file, and everything I see appears to have the correct path. I also don't see any / vs \ issues, however I feel I don't see the actual commands so who knows if it's using / or \ at that point. There are no spaces, case sensitivity looks good, I even had it regenerate some of the files like the batch file just to double check.

 

I think that with it showing the old graphic, what we are seeing is an issue with a cached copy of the old / original symbol. It seems like when I re-ran the symbol lib manager pointing it to the newer .lib, it simply didn't stick. I tried to re-run it and specify remove, of the zpuino core, however the core still showed as an option for me to select under the symbol tab. I don't see how this can happen unless there is a cached copy some where. Perhaps I need to flush the buffer some how. 

 

I can install this on a windows machine perhaps Wednesday and see if I'll have the same problem in windows. 

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Might I suggest that as an alternative that is likely not to cause such an issue, you learn enough of the VHDL syntax for creating a toplevel entity and architecture and declare components and instantiate them, this way you can use the same blocks that jack has for the schematic version but put them together using VHDL which is unlikely to suffer as many issues with its use.  The syntax can be a little strange however ISE can generate you an instantiation template of anything you want to use  and the other stuff it can generate when you create a source file, this leaves only wire signal declaration for you to do and specifying the signals that the component ports map to.

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Hello OmniTechnoMancer,

 

I certainly will look to learn more about VHDL, it's one reason why I look at this SOC effort. I'm certainly a NOOB to FPGA and learning this as I go. The schematic editor is a great way to help me get a feel for how the hipbone and leg bone connect before getting into the lower levels of VHDL. I think the concepts of doing it without a schematic is a bit different from Jack's goals. This thread title specifically notes with schematic editor. So I posted about some of the bumps in the rug I hit, and posted info such that these bugs can be ironed out. I think the issue is a mild schematic cache issue, I probably just have to click a button somewhere to flush the buffer. 

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I finally got ISE installed on windows 7, and got to compile this project. It seems to compile just fine on Windows, so I would agree with jack the problem seems to be a Linux issue. I would guess it's a / vs \ issue somewhere. I do see some oddities on both windows and Linux, in that I get these red box things on the right side of the symbol, however the red box things don't seem to be that much of an issue, the tracks route, and such. I wonder if these can be an indication of some underlying issue. I also wonder how to fix the Linux issue, perhaps I should create a new project and try to attach the files by hand. I kind of doubt that would work, as I suspect the issue is found in one of the sources.

 

Capture.png

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From the below, I see a symbol search path can be added to the sch2hdl command. I think the lack of this switch could be the problem, or at least one possible solution. Here's what I get when I run the below to get some help from this command.

/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64$ sch2hdl -h

Release 14.4 - sch2hdl P.49d (lin64)

blah blah

-sympath <sympath> A path to search for symbol files. There can be more than one of this switch

When I request a functional model in ISE, I get the below in the console. I notice the sch2hdl command does not have the above noted -sympath so to me it makes sense that it can't find the symbols.

Started : "View HDL Functional Model".

Running sch2hdl...

Command Line: sch2hdl -intstyle ise -family spartan6 -flat -suppress -vhdl Papilio_SOC_Base.vhf -w /home/jharvey/Desktop/papilio_SOC-master/gadgetfactory/Papilio_System_On_Chip/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch

ERROR: Failed to load symbols for /home/jharvey/Desktop/papilio_SOC-master/gadgetfactory/Papilio_System_On_Chip/example_SOCs/Papilio_SOC_Base/Papilio_SOC_Base.sch no netlist will be generated

ERROR: Could not find symbol "zpuino_empty_device"

ERROR: Could not find symbol "ZPUino"

ERROR: Could not find symbol "Papilio_Default"

I checked this on the windows machine, however it doesn't echo the command, so I don't know if this switch is used in windows. I did get an echo with a different command, which also did not include the switch. So I suspect the the symbol path is being done with an environment variable or something similar. I wonder how I verify the symbol path, or how I add it to that command.

Also to fix the red box issue, I simply drag the end of the wire over one box, and it re-attached correctly. So that's appears to be a minor problem.

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Hi all,

 

sorry for digging out this old thread, but it desribes exactly my problem. After downloading the latest schematc library 1.4 I tried to synthesize the VGA8 example project. I added the symbol directories as described by Jack in the C64 SID video and it looks all ok...

The OS here is Linux 64bit ISE is 14.7 (lin64).

Any ideas how to use the lib within Linux?

 

Many regards and silent xmas time

Peter

ERROR: Failed to load symbols for /home/peter/Programming/fpga/fpga/Papilio-Schematic-Library-1.4.1/Papilio_Schematic_Projects/Wing-VGA8/Papilio_SOC_Base_Papilio_One.sch no netlist will be generatedERROR: Could not find symbol "Wing_GPIO"ERROR: Could not find symbol "Wishbone_Empty_Slot"ERROR: Could not find symbol "Papilio_Default_Wing_Pinout"ERROR: Could not find symbol "Wing_VGA8"ERROR: Could not find symbol "VIDEO_zpuino_wb_vga_hqvga"ERROR: Could not find symbol "VIDEO_zpuino_wb_char_ram_8x8_sp"ERROR: Could not find symbol "ZPUino_Papilio_One_V1_hyperion"ERROR: Could not find symbol "clk_32to50_dcm"

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