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FPGA Hamster tutorials . Seven segment ans CASE problem.

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Hi all and thaks for the support and encouragement. Its nice to have friendly feedback (unlike some site forums that like to treat people who dont know absolutely f&&ng everything like twa*s. not mentioning any particular sites but I'm sure you all know some..)

 

But anyway back to the topic.I have read the chapters on speed and multiple files and am now experimenting with the seven segment display. I have manged to write a small program that involves turning on seperate segments and the decimal point via thre switches. The code is here:

 

 

entity segments_switches is

    Port ( anodes : out  STD_LOGIC_VECTOR (3 downto 0);

           sevenseg : out  STD_LOGIC_VECTOR (6 downto 0);

           dp : out  STD_LOGIC;

           switches : in  STD_LOGIC_VECTOR (3 downto 0));

end segments_switches;

 

architecture Behavioral of segments_switches is

begin

anodes <= "1110";

dp <=switches(7);

sevenseg(0) <= switches(0);

sevenseg(1) <= switches(1);

sevenseg(2) <= switches(2);

sevenseg(3) <= switches(3);

sevenseg(4) <= switches(4);

sevenseg(5) <= switches(5);

sevenseg(6) <= switches(6);

end Behavioral;

 

 

 

 

 

-- 0 = switches 0-5

-- 1 = switches 1-2

-- 2 = switches 0, 1, 3, 4, 6

-- 3 = switches 0, 1, 2, 3, 6

-- 4 = switches 1, 2, 5, 6

-- 5 = switches 0, 2, 3, 5, 6

-- 6 = switches 0, 2, 3, 4, 5, 6

-- 7 = switches 0-2

-- 8 = switches 0-6

-- 9 = switches 0, 1, 2, 3, 5, 6

-- A = switches 0, 1, 2, 4, 5, 6

-- B = switches 2-6

-- C = switches 0, 3, 4, 5

-- D = switches 1, 2, 3, 4, 6

-- E = switches 0, 3-6

-- F = switches 0, 4, 5, 6

The switch combinations for numericals from 0 to F are also there in comment. 

(The reason I didnt use the <> enter code tool above is because this is the 3rd time I have attempted to write this forum post. For some reason, the code entry window crashed on every second entry of a code example.)

 

Now I am trying to get the display to output numericals 0 to F according to switch combinations.

 

I am using the CASE statement and blocks of whens.

The code is below:

 


entity segments_switches is    Port ( anodes : out  STD_LOGIC_VECTOR (3 downto 0);           sevenseg : out  STD_LOGIC_VECTOR (6 downto 0);           dp : out  STD_LOGIC;           switches : in  STD_LOGIC_VECTOR (3 downto 0));end segments_switches;architecture Behavioral of segments_switches isbeginanodes <= "1110";process (switches)beginCASE (switches) ISwhen "0000" =>	sevenseg(0) <='1';	sevenseg(1) <='1';	sevenseg(2) <= '1';	sevenseg(3) <= '1';	sevenseg(4) <='1';when "0001" =>	sevenseg(1)<='1';	sevenseg(2)<='1';when "0010" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(6)<='1';when "0011" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(6)<='1';when "0100" =>	sevenseg(1)<='1';	sevenseg(2)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "0101" =>	sevenseg(0)<='1';	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "0110" =>	sevenseg(0)<='1';	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "0111" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(2)<='1';when "1000" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "1001" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "1010" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(2)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "1011" =>	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "1100" =>	sevenseg(0)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';when "1101" =>	sevenseg(0)<='1';	sevenseg(1)<='1';	sevenseg(2)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(6)<='1';when "1110" =>	sevenseg(0)<='1';	sevenseg(3)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';when "1111" =>	sevenseg(0)<='1';	sevenseg(4)<='1';	sevenseg(5)<='1';	sevenseg(6)<='1';end case;	end process;end Behavioral;

 

 

When I try to compile I get this message:

 

ERROR:HDLParsers:812 - "C:/Users/user/Documents/FPGA/we/work/segment_7_1/segments_switches.vhd" Line 145. A value is missing in case.

 

I don't understand what I am doing wrong..? Am I completely on the wrong track?? I have looked up the case reference on a few sites and in the XIlinx VHDL ref manual... Any help much appreciated. Thanks again lovely peeps. :)

Steve.

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Hi Steve, 

 

A STD_LOGIC (and each bit in a STD_LOGIC_VECTOR) can have more values than '0' and '1'. When you do a 'case' statement ALL values must be covered. Other states include undefined ('U'), error ('X') or high-impedance ('Z').

 

Change the last "when "1111" => " "to when others =>", and you will be back on track.

 

Yeah, it's stupid, but that is the way it works [shrug].

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Oh, and you never assign any '0's to your segments - once you have flicked a few switches all segments will be on!

 

You could cover it off with a "sevenseg <= (others => '0')" before the case, or change the assignment to be vectors (e.g. sevenseg <= "1110000"; )

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Hi Hamsterman. Thanks for the tip off. 9 values I believe. OK I have changed the last WHEN block to others.

It compiles but doesnt work on the hardware..?..

Apparently the switches have no load . Here's a warning.

WARNING:Xst:647 - Input <switches> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

And then physdesignrules about the switches' signals IBUF being incomplete so they are not actually being implenmented as a switch .Do I need to implement switches in a signal statement?


//NET switches(7) LOC = "P91" | IOSTANDARD=LVTTL;//NET switches(6) LOC = "P92" ;//NET switches(5) LOC = "P94" ;//NET switches(4) LOC = "P95" ;NET switches(3) LOC = "P98"  ;NET switches(2) LOC = "P2" ;NET switches(1) LOC = "P3" ;NET switches(0) LOC = "P4" ;//NET "clk" LOC = "P89" | IOSTANDARD = LVCMOS25 ;NET "anodes<0>" LOC="P18";NET "anodes<1>" LOC="P26";NET "anodes<2>" LOC="P60";NET "anodes<3>" LOC="P67";NET "sevenseg<6>" LOC="P62";NET "sevenseg<5>" LOC="P35";NET "sevenseg<4>" LOC="P33";NET "sevenseg<3>" LOC="P53";NET "sevenseg<2>" LOC="P40";NET "sevenseg<1>" LOC="P65";NET "sevenseg<0>" LOC="P57";//NET "dp" LOC="P23";

 

 

 I have tried changing CASE(switches) to CASE (switches(3 downto 0)) but to no avail.. Any ideas?

Is it the constraints file?

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Somehow the switches have now effect on the output, so have been optimized away. it will not be your constraints, but something going on in your vhdl process.

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Here's something similar from a completely different project - so all the values are wrong for you, and doesn't decode all values for data, but you should get the gist.

 

 

   process(data)
   begin
         case data is
            when "0000" => decoded <= "00111111";
            when "0001" => decoded <= "00000110";
            when "0010" => decoded <= "01011011";
            when "0011" => decoded <= "01001111";
            when "0100" => decoded <= "01100110";
            when "0101" => decoded <= "01101101";
            when "0110" => decoded <= "01111101";
            when "0111" => decoded <= "00000111";
            when "1000" => decoded <= "01111111";
            when "1001" => decoded <= "01100111";
            when "1111" => decoded <= "00000000";
            when others => decoded <= "10000000"; 
         end case;
   end process;

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I'm having trouble viewing this screen.?. I can only see half of your message above so I'm typing this one to free up space so I can see it. :)

I don't know if its my computer..?.

 

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I am not having any joy with this. I can't get it to work.

My brain isn't working.

Heres the code I have tried last.

 

 entity segments_switches is    Port ( anodes : out  STD_LOGIC_VECTOR (3 downto 0);           sevenseg : out  STD_LOGIC_VECTOR (6 downto 0);          -- dp : out  STD_LOGIC;           switches : in  STD_LOGIC_VECTOR (3 downto 0));end segments_switches;architecture Behavioral of segments_switches isbeginanodes <= "1110";process (switches(3 downto 0))beginCASE (switches) ISwhen "0000" => sevenseg <= "0111100" ;when "0001" =>	sevenseg<="0100000";	when "0010" => sevenseg <="1101101";	when "0011" => sevenseg <="1111001";	when "0100" => sevenseg<="0110011";	when "0101" => sevenseg <="1011011";when "0110" => sevenseg <="1011111";	when "0111" => sevenseg <="1110000";	when "1000" => sevenseg <="1111111";	when "1001" => sevenseg <="1111011";	when "1010" => sevenseg <="1110111";	when "1011" => sevenseg <="0011111";	when "1100" => sevenseg <="1001110";	when "1101" => sevenseg <="1111101";	when "1110" => sevenseg <="1001111";when others => sevenseg <="1000111";	end CASE;	end process;end Behavioral;

 

I honestly don't know where I am going wrong...

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OK I have it sussed.

I had to invert the 0s and 1s for the seven segment vector.

Code is here:

------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    19:24:58 02/01/2013 -- Design Name: -- Module Name:    segments_switches - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity segments_switches is    Port ( anodes : out  STD_LOGIC_VECTOR (3 downto 0);           sevenseg : out  STD_LOGIC_VECTOR (6 downto 0);          -- dp : out  STD_LOGIC;           switches : in  STD_LOGIC_VECTOR (3 downto 0));end segments_switches;architecture Behavioral of segments_switches isbeginanodes <= "1110"; process (switches(3 downto 0))beginCASE (switches) ISwhen  "1111" => sevenseg(6 downto 0)<=  "0001110" ;	when "1110" => sevenseg (6 downto 0)<="0000110";	when "1101" => sevenseg(6 downto 0) <="0100001";	when "1100" => sevenseg (6 downto 0)<="1000110";	when "1011" => sevenseg (6 downto 0)<="0000011";	when "1010" => sevenseg (6 downto 0)<="0001000";	when "1001" => sevenseg(6 downto 0) <="0010000";	when "1000" => sevenseg (6 downto 0) <="0000000";	when "0111" => sevenseg (6 downto 0)<="1111000";	when "0110" => sevenseg (6 downto 0) <="0000010";	when "0101" => sevenseg(6 downto 0) <="0010010";	when "0100" => sevenseg (6 downto 0) <="0011001";	when "0011" => sevenseg (6 downto 0) <="0110000";	when "0010" => sevenseg (6 downto 0) <="0100100";when "0001" => sevenseg (6 downto 0)<="1111001";when others => sevenseg (6 downto 0) <="1000000";	end CASE;	end process;end Behavioral;--dp <=switches(7);--sevenseg(0) <= switches(0);--sevenseg(1) <= switches(1);--sevenseg(2) <= switches(2);--sevenseg(3) <= switches(3);--sevenseg(4) <= switches(4);--sevenseg(5) <= switches(5);--sevenseg(6) <= switches(6);case switches (3 downto 0) is_ve-- 0 = switches 0-5-- 1 = switches 1-2-- 2 = switches 0, 1, 3, 4, 6-- 3 = switches 0, 1, 2, 3, 6-- 4 = switches 1, 2, 5, 6-- 5 = switches 0, 2, 3, 5, 6-- 6 = switches 0, 2, 3, 4, 5, 6-- 7 = switches 0-2-- 8 = switches 0-6-- 9 = switches 0, 1, 2, 3, 5, 6-- A = switches 0, 1, 2, 4, 5, 6-- B = switches 2-6-- C = switches 0, 3, 4, 5-- D = switches 1, 2, 3, 4, 6-- E = switches 0, 3-6-- F = switches 0, 4, 5, 6

 

Thanks again for helping. :) I'll be back soon....(lol)

All the best,

Steve.

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