Hans

ZPU question

Recommended Posts

This is not quite specific to the RetroCade Synth and if there is a better place to ask, please let me know. Is it possible to just set  tozpuino_number_io_select_bits to, say, 5, in order to have more Wishbone I/O slots, or does such a change require other reconfiguration?  In the RetroCade Synth hardware, most of the slots are already occupied and I would like to experiment with adding a few more SIDs or YMs.

 

Thanks,

Hans

Share this post


Link to post
Share on other sites

Well, this is a question for Alvie, he might not follow the RetroCade topic... If he doesn't respond here then we need to move the post to the ZPU topic so he sees it.

 

Jack.

Share this post


Link to post
Share on other sites

Hi Hans,

 

I'd suggest breaking one of these slots into subslots, because changing that setting would require changes in HDL, in bootloader and in IDE code.

 

This can be accomplished with a simple IO selector. You will however need to add some sort of new macro (like IO_SUBSLOT(X,y)) to properly access the registers.

 

Take a look at this one: https://github.com/GadgetFactory/ZPUino-HDL/blob/master/zpu/hdl/zpuino/wbmux2.vhd . Should be enough for what you need. Idea is to use a "select line" just below the top IO address select line.

 

I can help you with this if needed.

 

Best,

Alvie

Share this post


Link to post
Share on other sites

Good question, I was wondering about something similar myself.  

 

About how many gates do the ZPU, SID and YM cores take up? If you were to say, add another SID core, would you be duplicating it in its entirety  or would it be possible to reuse some of the blocks within each core to reduce the number of gates used? 

 

Thanks,

 

Brian

Share this post


Link to post
Share on other sites

Don't have the numbers for you right now, they actually depend on the FPGA used and how the synthesizer performs its optimizations.

 

But, regarding your concrete question, I think that with some effort you can at least reuse some small parts (like prescalers and such), but not much more, unless you rewrite the design (like having YM/SID to include more channels, but share all other parts).

 

Note that, with FPGA, there's no actual notion of "gates" - the basic building blocks are a bit more complex. Example: the 'apollo' variant uses 4384 LUT and 2745 Flip Flop, distributed across 3246 slices. BUT each slice (on S3E) can accomodate two 4-input LUT, and two FF (and they are grouped on CLB, each 4 slices.) But, due to design and timing, the number of occupied slices is greater than the "optimal" packing situation (for example, with those 4384 LUT, one could expect 2192 slices (each with two LUT), but this will probably cause timing issues for the router would have to use long paths in some situations).

 

Also, when timing problems are likely to occur, some design elements can be replicated, in order to achieve higher fan-out or to allow more easy routing. Routing (and fan-out) are the most problematic issues in FPGA.

 

Alvie

  • Like 1

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now