Lee O'D

Questions about current bit depth on audio mixing

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Hi, as usual I've got a bunch of questions...! I'm just trying to get my head around the current setup before I can then plan to contribute a bit more, sorry if it's annoying!

 

So i've been trying to look at the HDL for the various sound generators and mixers. Slightly confused with the multiple sigmadeltas and the audiomixer...

 

As far as I can tell, the audio mixer is working at 18 bit resolution (for the 3 inputs) with 20 bit accumulator for the output which of course is sigma delta'd into a 1 bit output. What's the clock rate of the final output currently?

 

The SID seems to also be 18 bit output which is good...

 

The YM (and POKEY) files seem to be 8 bit resolution output, but i couldn't see how this is mapped into 18 bits (or whether some implicit mapping to the more significant bits is taking place)?

 

For the MOD output, the render resolution seems to be 16 bits mono (filled to both channels), again not sure how this turns into 18 bits?

 

I'm also a bit confused by the zpuino_audiomixer.vhd vs the simple_sigmadelta.vhd files. If the audiomixer is providing the actual one bit conversion, is the simple_sigmadelta.vhd still used?

 

Also as another question, can you comment on the MOD frequency (defined in a couple of places, eg in Retrocade.h as #define FREQ 17000 //Freq for modplayer) - is this a compromise between the speed of the zpuduino running the rendering code and not sounding too low-fi?

 

Many thanks!!

 

Lee

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Hi, as usual I've got a bunch of questions...! I'm just trying to get my head around the current setup before I can then plan to contribute a bit more, sorry if it's annoying!

 

So i've been trying to look at the HDL for the various sound generators and mixers. Slightly confused with the multiple sigmadeltas and the audiomixer...

 

As far as I can tell, the audio mixer is working at 18 bit resolution (for the 3 inputs) with 20 bit accumulator for the output which of course is sigma delta'd into a 1 bit output. What's the clock rate of the final output currently?

The sigma delta runs off the 96Mhz system clock.

 

The SID seems to also be 18 bit output which is good...

 

The YM (and POKEY) files seem to be 8 bit resolution output, but i couldn't see how this is mapped into 18 bits (or whether some implicit mapping to the more significant bits is taking place)?

https://github.com/GadgetFactory/ZPUino-HDL/blob/POKEY/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/retrocade/papilio_pro_top.vhd

Line 1107 and 1108:

ym2149_audio_dac <= ym2149_audio_data & "0000000000";pokey_audio_dac <= pokey_audio_data & "0000000000";

 

For the MOD output, the render resolution seems to be 16 bits mono (filled to both channels), again not sure how this turns into 18 bits
I'm also a bit confused by the zpuino_audiomixer.vhd vs the simple_sigmadelta.vhd files. If the audiomixer is providing the actual one bit conversion, is the simple_sigmadelta.vhd still used?

 

Also as another question, can you comment on the MOD frequency (defined in a couple of places, eg in Retrocade.h as #define FREQ 17000 //Freq for modplayer) - is this a compromise between the speed of the zpuduino running the rendering code and not sounding too low-fi?

Alvie did the work on porting the ptplay library so I'm not 100% sure but this is how I think it works:

The ptplay library generates the digital audio stream, FREQ 17000 is used by the ptplay library to generate that audio stream at the correct speed. That digital audio stream is written to the registers of the zpuino_sigmadelta core:

https://github.com/GadgetFactory/ZPUino-HDL/blob/POKEY/zpu/hdl/zpuino/zpuino_sigmadelta.vhd

  sigmadelta_inst: zpuino_sigmadelta  port map (    wb_clk_i => wb_clk_i,wb_rst_i => wb_rst_i,    wb_dat_o => slot_read(5),    wb_dat_i => slot_write(5),    wb_adr_i => slot_address(5),    wb_we_i => slot_we(5),    wb_cyc_i => slot_cyc(5),    wb_stb_i => slot_stb(5),    wb_ack_o => slot_ack(5),    wb_inta_o => slot_interrupt(5),raw_out => sigmadelta_raw,    spp_data => sigmadelta_spp_data,    spp_en => sigmadelta_spp_en,    sync_in => '1'  ); 

I modified the zpuino_sigmadelta to not do any type of DAC but to instead just pass the digital audio data through, I then send that digital audio data into the audiomixer. (I did this because the audiomixer is not setup as a wishbone core yet, so there was no registers for the ptplay library to write its audio data to the audio mixer. I was in a time crunch so I took a shortcut here. We are going to want to update the audio mixer so it is a wishbone core and git rid of the zpuino_sigmadelta and just use the sigmadelta built into the audio mixer. )

 

The audio mixer takes all three inputs, combines them and feeds them into a deltasigma DAC:

Line 1091 in the master branch of https://github.com/GadgetFactory/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/retrocade/papilio_pro_top.vhd

   mixer: zpuino_io_audiomixer         port map (     clk => wb_clk_i,     rst => wb_rst_i,     ena => '1',          data_in1 => sid_audio_data,     data_in2 => ym2149_audio_dac,     data_in3 => sigmadelta_raw,          audio_out => platform_audio_sd     ); 

Look at the audio mixer code and you will see it is an 18 bit DAC that is driven by a 96Mhz clock.

 

Many thanks!!

 

Lee

 

 

Hope this helps.

Jack.

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