Sign in to follow this  
jbb

Timing constraints

Recommended Posts

I'm slowly working on my own (slow and basic) sdram controller while learning VHDL (I only did verilog before). I'm using a DCM block to generate a 100Mhz clock for my state model for this.

It worries me that I might try to do too much logic and signals won't be computed in time before the next clock comes along which obviously will break things. 

 

I assume this is what the timing constraints are for though? To verify that your design will work at the speed of the clock. But I can't find any information about how to add constraints saying that a specific signal is generated using the 100Mhz clock rather than the 32MHz standard clock for example so the logic needs to be fast enough to work for that.

Or rather I can find lots of information. Too much... And I don't know where to start. Can anyone either help me out with how to set up suitable constrains, or point me at an introduction to how to do this rather than the hundreds of pages of documents that tell you everything at once. (Which obviously I'll read once I understand the basics)

Share this post


Link to post
Share on other sites

In your constraint file add something like " | PERIOD = 31.25ns" to the clock constraint - e.g.:

 

NET CLK         LOC="P94"  | IOSTANDARD=LVTTL | PERIOD = 31.25ns ;

 

Build your project, and then check your "Final timing score" on the "Summary" report./ A value of Zero means the timing constraints has been met.

 

The DCM component can pass the constraint through from the 32MHz section to the high speed section, with the smaller period value (e.g 10ns for 100MHz).

 

Also, remember to turn "Pack I/O Registers/Latches into IOBs" setting in the "Map Properties" to ensure minimal signal skews., and don't have any logic between the registers holding the values for signals and the outside world - otherwise signals will have skews.

Share this post


Link to post
Share on other sites

Thank you for that. 
Ah, I wasn't aware that the DCM component was clever enough to pass through the timing, that makes sense though.

Thank you for the advice on the pack I/O properly. It seems it was already turned on so I assume it's the default, but defintatly worth checking!

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this