magnusk

Pipistrello - "Papilio on steroids"

66 posts in this topic

We're almost finished with 1.5.X port for ZPUino also :)

 

mkarlsson: Question for you: do you have size figures for Microblaze with some IO devices, and relevant configuration for it ?

 

Alvie

I looked at the report and it said " Number of occupied Slices: 2,367 or 34% of the LX45.

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It's looking good so far, I just got a sample board from Magnus, it is really nice by the way. We are submitting the design to get pricing first so we can see how feasible this project is, I think this will work out just fine though.

 

Jack.

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I looked at the report and it said " Number of occupied Slices: 2,367 or 34% of the LX45.

 

how large are the caches ?

 

I'd really like to take a look at the map report (verbose one), can you send it to me if you have it ( alvieboy@alvie.com ) ?

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Magnus dropped a hint that he assembled it in his basement... his basement must be tricked out!

 

BGA is actually not *that* hard to work with once you learn a few tricks. The biggest issue is that unless you have access to an xray machine, it's very difficult to tell whether all has gone well and you risk ruining an expensive part.

 

I've done a limited amount of rework and had success with my homemade hotplate, a liberal smear of liquid flux and precise alignment markings on the PCB. One of these days I'll have a go at assembling a BGA board from scratch but multilayer PCBs are a heck of a lot more expensive than double sided, just for the blank board.

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Well, hopefully there will be no more need to build boards "in the basement", the first batch of boards from the assembly house in Austin, TX are in and they look fantastic.

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On all the pictures the connectors for the Papilio wings are not fitted, are those on the new boards? I'd love to have one of those with the arcade mega wing

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Be careful what you wish for! A design using just the programmable logic (650 LUTs,  220 registers, and a frame buffer of block ram) takes 16min32 to build a new bit file. 

 

However, If you really are after a Zynq board, keep an eye on http://parallella.org. The amount of engineering that has gone into that board is amazing - 12 layers... 

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That also would depend on the computer running the tools? what would happen on an 2x quad xeon with 56GB ram, would that help on build time?

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In my experience the Xilinx tools are crap at taking full advantage of resources or parallelism. I have 8 cores and 32G RAM and simulations still run slow as. So much so I can actually run two or sometimes even three simulations while also watching a movie on the same PC to pass the time while waiting for the simulations to run for 20-30 minutes and the CPU cores are hardly loaded while most RAM is unused.

Oh speaking of RAM there's been a memory leak present in ISE since like forever. After doing multiple compilation runs I can see more and more memory being used and not released after each compilation completes. After a while the compilation runs noticeably slower while ISE ends up holding onto half gig of RAM. After closing ISE and re-opening, the memory is released and compilations run fast again.

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Hamster,

 

Wow, that sounds painful...and I'm using a VM to boot :) Admittedly, A Zynq would be way over my skill level, but it reminds me of a Cypress PSoC, which has been really enjoyable.

 

I did see the Parallella KS campaign. Unfortunately, I wasn't able to participate, but I'm on the waiting list. That looks like an incredible system.

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Be careful what you wish for! A design using just the programmable logic (650 LUTs,  220 registers, and a frame buffer of block ram) takes 16min32 to build a new bit file. 

 

However, If you really are after a Zynq board, keep an eye on http://parallella.org. The amount of engineering that has gone into that board is amazing - 12 layers... 

 

 You were using ISE or Vivado ?

 

They say Vivado is very fast.... but since Parallella is not yet out, I don't have any Zynq board.

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