fiddler

Diagnostic Test in the FPGA

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It dawned on me that I can basically have built in test "software" in the FPGA as I can monitor any io in parrallel in real time with no additional overheads. NOW that is cool.

This is to monitor my program, the outside io's, NOT the FPGA itself.

This could be read out to a screen, JTAG port or whatever.

I have traweled Google but haven't found anything of any significance.

Can anyone shed some light on this, share any experince or maybe provide a link or something.

Anything is appriciated

Cheers

K

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Fiddler,

Take a look at the Sump Blaze Core, it's the logic analyzer core that is used in the OpenBench Logic Sniffer. If you have enough BRAM you can embed this Sump core in your project and have a full blown logic analyzer that outputs over the serial port.

Jack.

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One option could be to just 'echo' the signals of interest down the RS232 port to the host. You can get around 3Mbits/s....

I'm thinking of designing something that when in "armed" state captures 8 or 16 channels into Block RAM at full speed, when a trigger event occurs it captures another n/2 samples then squirts them all down the serial port as ASCII hex followed with a NL, and then reset into 'armed' mode.

It would then be pretty easy to read this input and display it in a cheap and nasty character-mode interface.

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