Jack Gassett

Prototype: LogiStart MegaWing

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Ok, there is either something wrong with the pin converter tool or I'm doing something wrong with defining the new Wing, I'll ask Kevin about it. I just uploaded a corrected ucf file to the download section, here's what the corrections look like:

NET LED(7) LOC="P17" | IOSTANDARD=LVTTL; # C15

NET LED(6) LOC="P16" | IOSTANDARD=LVTTL; # C14

NET LED(5) LOC="P15" | IOSTANDARD=LVTTL; # C13

NET LED(4) LOC="P12" | IOSTANDARD=LVTTL; # C12

NET LED(3) LOC="P11" | IOSTANDARD=LVTTL; # C11

NET LED(2) LOC="P10" | IOSTANDARD=LVTTL; # C10

NET LED(1) LOC="P9" | IOSTANDARD=LVTTL; # C9

NET LED(0) LOC="P5" | IOSTANDARD=LVTTL; # C8

NET SWITCH(7) LOC="P4" | IOSTANDARD=LVTTL; # C7

NET SWITCH(6) LOC="P3" | IOSTANDARD=LVTTL; # C6

NET SWITCH(5) LOC="P2" | IOSTANDARD=LVTTL; # C5

NET SWITCH(4) LOC="P98" | IOSTANDARD=LVTTL; # C4

NET SWITCH(3) LOC="P95" | IOSTANDARD=LVTTL; # C3

NET SWITCH(2) LOC="P94" | IOSTANDARD=LVTTL; # C2

NET SWITCH(1) LOC="P92" | IOSTANDARD=LVTTL; # C1

NET SWITCH(0) LOC="P91" | IOSTANDARD=LVTTL; # C0

Thank you for the heads up!

Jack.

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Sadness grips my heart. I tried to buy one of these LogicStart boards from the gadget factory store and I got the message that they're out of stock. Is there an ETA on when more might arrive? I can get by without it, but it seems so convenient (and a good value).

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Hello Johnj,

Hopefully we can release the sadness that grips your heart this week. :)

There are 50 boards that should be arriving any time now, we have to do a little soldering to get them ready but it should not take long. I'm hoping to get them back up in the store very soon, when we do there will be an announcement to the Gadget Factory blog and I'll respond here too.

Thanks!

Jack.

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I've been using Logicstart with "FPGA Prototyping by Verilog Examples" and with many simple projects on the web. Adjusting the constraints is all I've had to do to adapt. The only thing I'll miss is some kind of RAM for learning projects involving memory controllers. Maybe I can get by with building the RAM and the controller in the FPGA just for the learning.

In brief, thumbs up for Logicstart and Papilio. They're great.

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Johnj,

The Papilio Pro board is going to be ready at the end of November, so you will soon have the option to pair the Papilio Pro with 64Mb (8MB) of SDRAM with the LogicStart board!

Jack.

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Hi Jack,

 

I went looking for a cheap logic analyser and found the OpenBench Logic Sniffer. Puzzled by the Butterfly connector, I've now also got a Papilio one 500K and LogicStart board What a nice piece of kit, particularly with Mike's Intro PDF !

 

However I found a little issue as I wanted to get the colon and decimal point running on the 7seg, noted it wasn't wired, fixed that on my wing via a bit of resource sharing..

 

I have noticed however that there are no current limiting resistors on the 7segment display and it gets really hot - for example when trying to get things running without switching segments, this will limit the life of the display.

 

I've found your updated V2.1 board designs on github with the limiting resistors fitted, however on your change log, you do not indicate the change of the joystick to be shared with the slide switches.

 

I'm also wondering if there will be a revised PDF with the differences with the new RGB LED, stereo output, etc, plus warnings about change of use of the joystick pins on the connector, since this could result in people damaging their outputs if they wiggle the joystick as they would be shorting those new outputs to ground.

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Hello timc,

 

We are still testing the prototypes with the changes that you saw, we ran into some issues with the RGB LED and had to do another round of prototypes. So the new design is still in flux and testing right now, but once we get everything nailed down and the updated design submitted for manufacturing we will definitely be updating the documentation to reflect the changes.

 

Thank you for the note about your concerns about the shared joystick pins, I'll review things with my partner Girish who is driving the changes for resale in the Indian market.

 

Thanks!

Jack.

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Jack, Just let me know when things are sold enough for me to order a Rev 2.1, and I'll make a new copy of the Guide.

 

I'm just wondering if I should remove the Basys2 stuff, and if it is worth while making it include the Papilio Pro... any suggestions would be gladly welcome.

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Please include the Papilio Pro. *Especially* if you include something using the SDRAM.

 

I have no opinion on the basys2 stuff, I got pulled into this world via the Papilio. I have no idea how popular those boards are.

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Hello,

The LogicStart v2.1 prototypes are almost ready - I was waiting for new RGB LEDs with relatively lower V(f) since we operate them at 3.3V directly and adding a driver would add to cost and complexity. We can always make a special RGB LED matrix Wing or Megawing for more serious and specialized work with those.

The board is not 100% compatible with earlier versions, although most functions can work with a minimal change to the ucf file and/or change of IO references in the application. The changes are:

  • activation of additional LEDs - colon in the middle (for clock display) and the apostrophe after the third digit (useful for displaying temperature as "°C" or "°F") by way of adding the 5th digit select signal AN(4)
  • addition of a RGB LED
  • stereo audio instead of mono
  • support for Grove style sensor boards (analog only) - 3 pin headers with VCC-GND and signal provided for each analog input
  • Current limiting resistors added for 7-segment display (earlier version relied on FPGA's internal current limiting)
  • In addition to this, we will scale back the ADC to 8-bit 200ksps which costs less than half of 12-bit, 1Msps version. Most beginner level projects will not need all that speed and resolution. All the devices in ADCxx8Syy2CIMT (xx is resolution: 08/10/12 bits, and yy is speed: 02 = 200ksps, 05 = 500ksps, 10 = 1Msps ) are pin-compatible, so we can provide any of the variants for specific orders. The software or SPI IP for ADC interface will not change as ADC data is shifted 2 or 4 bits to the left so MSB is always bit 11 whether the ADC is 8, 10 or 12-bit.


The joystick shares 5 pins with the switches, so when using the joystick these switches will have to be moved to top position and 3 switches (SW0~2) on the left are available to set config or use as jumpers. Pull-ups are added to allow the joystick to change the signal level. Both the switches and joystick buttons are in parallel, so there won't be any damage but the inputs will be stuck at '0' if the switches are at wrong position and the joystick won't respond.

The pin usage is changed to have all the switch signals near the joystick's - 8x LED and 8x switch banks are swapped.

Moving the joystick wires to share with the switches frees 5 IOs which are used as follows:

  • 1 for additional audio channel
  • 1 for additional digit (5th) enable to use the colon and apostrophe
  • 3 for the RGB LED


Please see the attached ucf file for the new version.

Girish
 

Papilio1_LogicStart2.ucf.txt

post-32023-0-59061700-1357665609_thumb.g

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As you are doing an uplift, is it possible to straighten out the contradictary labelling of the connector designations in the documentation - Possibly by adding row A, B, C designators to the silk screen on the wing connectors - to reflect those already on the FPGA board. 

 

The wing pinouts defined here http://papilio.cc/index.php?n=Playground.PapilioPinouts matches the FPGA board, but contradict with those listed on the LogicStart MegaWing circuit diagrams - columns A and B are reversed on the pinned out connector to the right of the SPI ADC, but right on the Power block shown below - this makes it more confusing when mapping functions to real pins.

 

For info, if anyone wants to use my hack to enable the dots on the 7seg display on the older 1.2 board, I shared the VGA RED0 pin to drive an extra PNP transistor with an otherwise identical layout to that used in the V2.1 board's layout for the additional 7 segment drive, except the current limiting resistor was in the collector leg of the transistor.

 

My logic being that I probably won't end up using both VGA and 7segment and even if I did, then there is sufficient drive from the FPGA to do both without affecting functionality.

 

Similarly, other VGA RGB pins could be borrowed for other functions. I plan to add an RGB LED function later using a similar approach as used on the 2.1 board.

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and the labeling of the switches and leds will be correct regarding msb-lsb?

 

 

Any upgrade path for us already having the previous logicstart? :D

It looks like Girish has indeed changed the numbering of the switches so it has SW7 on the left side instead of the right side. I will have to think about any kind of upgrade path for existing LogicStart owners.

 

As you are doing an uplift, is it possible to straighten out the contradictary labelling of the connector designations in the documentation - Possibly by adding row A, B, C designators to the silk screen on the wing connectors - to reflect those already on the FPGA board. 

 

The wing pinouts defined here http://papilio.cc/index.php?n=Playground.PapilioPinouts matches the FPGA board, but contradict with those listed on the LogicStart MegaWing circuit diagrams - columns A and B are reversed on the pinned out connector to the right of the SPI ADC, but right on the Power block shown below - this makes it more confusing when mapping functions to real pins.

 

For info, if anyone wants to use my hack to enable the dots on the 7seg display on the older 1.2 board, I shared the VGA RED0 pin to drive an extra PNP transistor with an otherwise identical layout to that used in the V2.1 board's layout for the additional 7 segment drive, except the current limiting resistor was in the collector leg of the transistor.

 

My logic being that I probably won't end up using both VGA and 7segment and even if I did, then there is sufficient drive from the FPGA to do both without affecting functionality.

 

Similarly, other VGA RGB pins could be borrowed for other functions. I plan to add an RGB LED function later using a similar approach as used on the 2.1 board.

I see the problem you are talking about with the schematic, I can update that pretty easily in the library to correct the row labeling. We will put it on the task list to add row labels to the final PCB layout. Please take a look at the LogicStart Wiki Page, I added tables for each hardware section that makes it very easy to find which FPGA or Arduino pin connects to each of the LogicStart MegaWing pins. I will add it to my todo list to update those tables for the Papilio Pro.

 

Jack.

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kinda joking on the upgrade path idea, but, is the old ADC pin compatible with the one that is selected now?, if I want to keep the 12bit, 1mbps, or would it be possible to order it with that one?

8bit is kinda on the low side, but of course, since this is primarily an learning tool..

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The ADC's are pin compatible, but it probably won't be possible to offer different options for the ADC, it's just too expensive to try to manage different manufacturing options. It seems like its a herculean task to bring a board like this to the market as it is, trying to bring multiple versions of the same board makes it even more difficult... Maybe down the road when we get more resources and can afford a decent pick and place machine and someone to run it we can start doing custom, low run batches of custom configurations...

 

Jack.

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For sure! I'll even help teach you the best technique if you want, Papilio is all about hacking. :)

 

Overview of how to do the soldering:

  • Use the hot air station to remove old chip. (Tip: use plenty of flux from a flux pen to make the job easier.)
  • Use flux pen and solder wick to clean up the pads
  • Soldering the new chip on has a couple options:
    • Use solder paste and hot air station:
      • Put solder paste on the cleaned up pads - don't worry about how much you put on, just draw a line across the pads.
      • Align new chip and hold it in place with dental pick while you use your hot air gun to melt solder paste.
    • Use regular solder and soldering iron - even a cheap iron works
      • Apply flux to the pads and pins with your flux pen.
      • Align your new chip and hold in place with dental pick. Put a little solder on tip of iron - then tack two corners of chip onto the pads.
      • Add solder to pins on opposite sides that you tacked - then use the drag technique to drag the solder across all pins/pads.
  • Cleanup - Do this no matter what method you used
    • Use the drag technique to get all excess solder onto one side of the chip, then use a solder wick to wick up the excess solder.

Jack.

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Sounds like fun!, I have already tried to remove various chips with the hotair, seems like it's working well. Not soldered any small chips like this yet, but have an smd kit to assemble, going to try that first.

But first need to get the new logicstart, sometime this spring/summer?

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In the good ol' days, chips came in sockets and you popped one out and dropped a JEDEC pin compatible one in. I guess the fact that we can't do that today is called evolution. :-(

 

Seriously though, engineers don't make good accountants, keep the higher spec ADC and increase the price. After all if its about functionality and learning, then it needs to be useful and relevant too. If you're really set on providing different options, make a microwing / picowing (small DIL socket layout - like SparkFun / AdaFruit / SKPang do) and allow people to choose what they want most, then an ADC could be a DAC, or something else.

 

On the compatibility of V1.2 to V2.1 boards, if I've understood FPGA's properly, then presumably you just have two constraints files, one that maps to the V1.2 and one that maps to the V2.1 layouts, does it actually matter where they physically come out ? Prioritise the innovation, not the backwards compatibility, capitilise on the flexibility of the FPGA's. Could you for example detect board version by the presence of the 5th transistor / second audio channel RC component / LED using existing capacitance / resistance to show ability/inability to drive and sense change on that pin. Alternately can we do conditional if/case in constraints files based on an input constant "BoardRev"

 

If not get people reading the text version number of their board to determine functionality, like they would have to on a data sheet for different device revisions or if they used different standard wings on different wing ports

 

Alternately, if you want to start again, call the new board something funny like the LogicStartAgain or LogicStartReloaded / Rebooted. Product evolution happens, capitalise on it.!

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Well, I guess we can provide 2 versions of the board - one with the lowest end device and other with the highest end device in the family of 9 variants. We scaled the ADC back because we wanted to make the board affordable for students, especially in India. We are also working on lowering the cost by alternate sourcing of some high value parts.

 

So it may be possible to offer a board with 8-bit 200ksps ADC or 12-bit 1Msps ADC - the price differential would be around $5.

 

I did miss mentioning the reversed labeling of switches and LEDs, they are meant to assist students in working with binary numbers with for example, the adders and shift register experiments. But then, its FPGA - you can simply put stickers on them relabel them with permanent markers and use the old numbering internally. You will still have to swap the groups of 8 pins though.

 

About detecting the Wing/Megawing - Jack and I had a brief discussion long back (he may not even remember) about adding a I2C EEPROM to each Wing and perhaps a RESET signal (we still have space for 4 pins in the power row of the wing) but that would be too taxing on the FPGA which had already run out of IOs. And it opens another can of worms, when the one uses multiple Wings of the same type, it will need some jumpers, or hardcode a binary value on 1 or 2 pins per Wing slot to set the device address and so on... Figure we don't require all that since this is an engineer's tool, everything does not have to be automated and self-configuring.

 

I agree that backward compatibility is not the priority here, but then we also have to build upon existing work so that we don't have to start over again. I believe just by swapping the LED/Switch IOs in the ucf file and changing references for joystick inputs (if using joystick) in the application, everything will work correctly with existing projects meant for v1.2

 

Girish

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Hi Girish, I think all your ideas are excellent. The market for low end FPGA dev boards is pretty price sensitive, so removing > 10% from the price of the LogicStart is excellent - after all, 8 bits of resolution should be enough for anybody :-)

 

I would suggest rather than having two versions of the Logicstart, focus on getting the LogicStart v2 completed, then consider making a "LogicStart Pro". 

- Remove VGA and replace it with HDMI 

- upgrade the 8-bit DAC to a 12 ADC

- Add a audio DAC

- Maybe add a USB connector?

I feel that this would be an excellent paring to the Papilio Pro, esp when Linux is up and running on it.

 

Without knowing what I am talking about, the "LogicStart Pro + Papilio Pro" would be approx $125, where as the  "New revision LogicStart + Papilio One 250k" is about $75.

 

If they are not top secret, I'm really interested to hear how you will get these boards in front of students, and at what level of education. I've been trying to get a few locals where I live to show some interest, but am finding it hard to get any traction. It would be an excellent for Gadget Factory if you are able to get the Papilio platform into the classroom. Email or message me privately if you like

 

Mike

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