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Testbench for the SRAM module.

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I've written a test bench that simulates the first 32 bytes of the SRAM.

It also logs (to the iSim console) if the following occurs:

when the write enable pulse is too short

  • when  the data setup times for a write is too short

  • when  the address bus changes when write enable is active

  • It outputs 'X's during the access time, allowing you to see when you capture data before it has settled.

Find it at 

Hope it helps somebody

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Had a look at that pages you linked to - makes mine look quite primitive!

Thanks for the excellent link - things like that very hard to find in Google. You find lots of talk but no code!

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