Guest monkeydoo

FPGA radio

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Guest monkeydoo

Hi

First post! I hope this is the correct place to post.

Just thought I'd post some details of my first FPGA project.  It's a software defined radio reciever using the Papilio One 250k board.

Basically, I've interfaced a 10MSPS ADC with the FPGA adding a RF front end.  Implmented inside the FPGA is all the glue for the ADC and a digital down converter (complex mixer).  It's got a variable CIC decimation filter and half band FIR. 

The resulting I/Q samples are sent back to the PC via a 3Mbaud UART.  Currently the Q samples are discarded due to the lack of bandwidth.  This results in no opposide sideband rejection.  I need to implment a higher speed interface to the PC.

A small application has been written to talk to a state machine that controls the recieve frequency and decimation ratio.  The eventual idea is to get this intergrated with GNU Radio.

The ADC is only clocked at 5MHz at the moment.  Therefore the tuning range is 0-2.5MHz.  I can hear lots of AM broadcast stations in the correct places, plus lots of aliased in stations from higher bands.

Even only with the 250k board, only 33% of resources are used.

The board is very 'rough' due to alot of hacking to get it working.  I suspect it's as deaf as a door nail due to the high noise floor and I don't own any test equipment!

A short video showing it in action.

http://www.youtube.com/watch?v=rpIIef4bqfI&context=C30a261bADOEgsToPDskIhkosFJoWKuRBhvLeP6cT7

Cheers,

Ian

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Now this is wicked cool! Amazing work so far, this type of project is really exciting. :)

Basically, I've interfaced a 10MSPS ADC with the FPGA adding a RF front  end.  Implmented inside the FPGA is all the glue for the ADC and a  digital down converter (complex mixer).  It's got a variable CIC  decimation filter and half band FIR. 

Can you share which ADC you used? We have been talking about making a nice ADC Wing.

The resulting I/Q samples are sent back to the PC via a 3Mbaud UART.    Currently the Q samples are discarded due to the lack of bandwidth.    This results in no opposide sideband rejection.

Are you using the Xilinx UART core from the Picoblaze project for this?

  I need to implment a  higher speed interface to the PC.

If you don't mind working with experimental hardware we have a high speed USB Wing designed, but have not had any time to build it or test it out. (Actually I think Girish may have built one and played with it some.) I have PCB's on hand and if you send an email with shipping info to support@gadgetfactory.net I can send a PCB to you.

I'm going to schedule a blog post about this so anyone else who is interested can join the discussion here. I'm sure that there are plenty of people who would be very excited to follow your progress and help out along the way.

Great work!

Jack.

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Guest monkeydoo

Hi Jack

Thanks!

The ADC I'm using the AD9220 from Analog.  It's 10MSPS 12-bit parallel, so really easy to work with.  I'm just clocking it from a DCM and it seems to behave.  Although, I am having a problem getting the input range set correctly from the internal reference.  It doesn't seem to behave as the datasheet describes.

Yes, I am using the Xilinix UART core from Picoblaze just like in your tutorial. I feed the samples into a FIFO with independant read/write clocks and the UART reads them back out.

I'd be really interested in that PCB.  I've seen a post somewhere about it being in development.  I've been patiently waiting for it :)

I plan to put a project page together with schematics etc soon.

I'll drop you an email later regarding that board..

EDIT:

I've uploaded a better video showing the hardware tuning around the MW band with GNU Radio.

http://www.youtube.com/watch?v=848gDw_Ib7o&context=C370c1bcADOEgsToPDskIhkosFJoWKuRBhvLeP6cT7

Cheers,

Ian

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2012 starts very good :D. I'm really impressed of your work Ian and would really appreciate if you could keep us up-to-date... facebook would be great for me!!!

I stop my plans buying a pegasus!!!!!! Very exciting

All the best for2012

Peter

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Greg just posted a blog article about this thread on the front page, check it out.

FPGA Radio Project

So we are all eagerly awaiting any news on your progress. :) You have us on the edge of our seats.

Jack.

BTW, we have a Facebook Page and are looking into crossposting the blog there in case anyone wants to discuss it there too.

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Guest monkeydoo

HNY Guys

I've been designing a new board based around a faster ADC.  The current board was just a quick lash up to test the DDC (digital down converter) in the FPGA.

I'm still waiting on the parts arriving.  I will be using an AD9226 12BIT ADC (65 MSPS) and a AD8369 which is a digitally controlled variable gain amplifier.  Its gain/attenuation is controlled from a 4 bit bus from the FPGA.  I must also now look at using an external clock source.

Just for fun I overclocked the 10 MSPS ADC to 30 MHZ.  It worked as well as could be expected... I was able to hear very strong European stations up on the 20m band (14MHz) with an indoor dipole.  I estimate the MDS to be very poor due to the ADC being stuck in the wrong input range.  All the small signals getting quantized away by the ADC....

I've also written a plugin for a popular piece of SDR ham radio software on Windows called WinRad (www.winrad.org).  It can control the receive frequency and feed the application the audio samples from the UART.

If you've haven't guessed by now... I'm a licensed amateur radio operator hence my interest in this type of project.

Thanks for all the interest.. 

Cheers,

Ian

EDIT: Typos

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Guest monkeydoo

Hi Jack

I'm using 2 of the 4 available DCMs in the current design. 

From what I've read, sending the DCM output out through an OBUF (skew/jitter wise) isn't a good idea.  XSE certainly complains about it.  If anyone can offer any advice I'd appreciate it.

My plan was to use an external 64 MHz oscilllator fed into a 1:2 low skew clock buffer feeding both the FPGA and ADC.

Ian

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Try using an ODDR flip flop. Use both DCM clocks (0 + 180deg) or a local inverter to clock the ODDR, and tie their values to '1' and '0'.

This is how clocks are generated for DDR on most designs.

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Guest monkeydoo

Try using an ODDR flip flop. Use both DCM clocks (0 + 180deg) or a local inverter to clock the ODDR, and tie their values to '1' and '0'.

This is how clocks are generated for DDR on most designs.

Ahh.  Thanks, this is exactly the nugget of information I was missing.

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Guest monkeydoo

Just a small update. 

I've built the board based around the faster AD9226 ADC.  It does "work" but still the VERY high noise floor (about -60DbFS) .  The good news is without an antenna connected the NF is exactly where it should be. 

This in my mind means it's likely it's a matter of input filters now.  I suspect wideband noise is being aliased back in. Especially the FM broadcast band as there is currently NO low pass input filters. I was concerned for a while it was a "hash" of digital noise coming from the FPGA and FTDI chip but the board layout seems quiet enough for my purposes.

I've also isolated the RX DDC component of the USRP1 + 2 firmwares and ported both to the Papilio.  I've dumped my original code in favour of this.

I have learned a great deal so far and the next board will move to a 14bit ADS5500.  There is a couple of new short videos in my YouTube channel showing some CW on the 10M band and SSB up on the 20M band

Cheers,

Ian

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Guest monkeydoo

Yes, I agree.  Generally 14bit ADCs capable of > 30 MSPS are expensive.

The ADC1010S you mention is obviously fast enough but doesn't have enough bits.

In this type of reciever you need high dynamic range and high sensitivty.

Do the maths with a 2v pk-pk input range:

2*0.707 / (2^10) = 1.3mv

vs

2*0.707 / (2^14) = 86uv

Gain in front of the ADC needs to be kept to a minimum to maintain dynamic range.  To put these figures in context a typical strong signal of S9+10db is 160uv.  A weak signal arriving at the antenna could be as small as 0.3uv

10 bits just won't cut it.  12 bits as I'm currently using is barely enough.

***EDIT 11/02/12:

Thought I'd share this.  This screenshot was taken during a RTTY contest on the 14 MHz band. 

I've measured the sensitivity with a signal generator and it's easily the 80uV range.  You see a mirror image across the band because the Q samples are still being discarded.

rtty2.png

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Guest monkeydoo

Jack,

I will make the final design available freely.

Thanks, the PCB arrived in the mail today.  I'm waiting till I've finished my current board layout so I can order all the parts at once.  Are these boards from BatchPCB? The quality looks very good!

I'm going to try out BatchPCB with my new board.  Though I've been forced to learn Eagle so I can get proper gerbers.  Up until now I've always used ExpressPCB and just etched at home.

I wonder if anyone on the forum would be willing to cast their eye over my gerbers after I get them through BatchPCB's DRC ?

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Sounds great,

Those boards are from batchpcb, I also use Seeed Studio's Fusion service. If I want to make the boards available for other people to buy then I use batchpcb. But if I want more boards for cheaper then I use Fusion...

I'd be happy to review the design's gerber files when they are ready. I also recommend that you download the free version of viewmate. It is well worth the effort to import all your gerber files into viewmate and take a look at all layers before you submit a design. A CTL-F4 when viewmate opens will let you choose a directory with all your gerbers in them. Doing this is usually the best way to spot some silly error on your silkscreen or with a part placement.

Another tip, use the cam file from Seeeds Fusion service to generate your gerbers. And finally, I always go through the tutorial from Sparkfun and check all the points in my design. The part about tenting vias is a very good one.

One last, last thought. Always inspect your ground plane and make sure it didn't accidentally get broken somehow. :)

Hope this helps,

Jack.

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Oh, one other thing.

Circuit cellar had a great article about making High-Speed PCB's in issue 253. It was the article titled "THE DARKER SIDE—RF and High-Speed PCBs: How to Avoid Basic Mistakes, by Robert Lacoste, p. 64"

Might come in handy for the board you are working on.

The gist of it is to make a very solid ground plane and use vias to box in any areas that you don't want noise to escape from.

Jack.

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Guest monkeydoo

Thanks some good advice there.

To be honest im not all the worried about the layout at this stage.  Serious RF engineers would laugh at the thought of 100 MHz being high speed.  I once was told < 500 MHz is just "wriggly DC" :)

The ADC is driven differentially so tends to reject a lot of the common mode present at the PCB level.  Phase jitter on the other hand from the clock will set the noise floor hard.  The ADC requires really low phase jitter from its clock (<700fs) to achieve decent performance.  This is my concern at the moment.

Cheers,

Ian

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Guest monkeydoo

@Jack

I tried to assemble the High Speed USB Wing tonight.  I had a few problems:

There are a number of items missing from the Mouser BOM such as the load capacitors for the crystal. (I never checked it!)

The EEPROM footprint does not match the part in the BOM

It was very difficult to solder the through hole components such as the crystal due to solder resist covering the holes on the underside of the board.

So only a basic smoke test was carried out.  Windows didn't enumerate the board when connected likely due to the crystal not oscillating.

Cheers,

Ian

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Ian,

Thank you for the update and sorry for the issues. :)

I should have put on the link to the Mouser BOM it is unverified... I know we started doing that at with later BOM's we made but the USB Wing was an early one. The BOM was put together as a training exercise for someone new to the team and since I never actually built any Wings I never verified that it was right... Sorry.

Hmmm, solder resist on the bottom huh? I'll have to look closer at the board... That's odd, I think it was my first time using Seeed's gerber CAM's so maybe something needs to be tweaked there.

I know Girish built up some boards and got them to work, maybe he can provide some pointers...

Jack.

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Guest monkeydoo

No worries.  The link on the the playground page did state the BOM was unverified.

Having a quick look at the schematic, all that seems to be wrong is due to my missing R1.  The FT232H just isn't getting pulled out of reset :)  I hope to get the missing parts soon.

Here is what I believe to be missing from the BOM:

R1 - 1K 0603 resistor

R4 - 4.7K 0603 resistor

R5  10K 0603 resistor

R3 - 2.2K 0603 resistor

C9,C10 - 0603 27pf capacitor

C6 - 4.7nf 0603 capacitor (tant?)

U2 doesn't fit.  I am not sure what package U2 is.  The part in the BOM is too large (SOIC-8).

Cheers,

Ian

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Guest monkeydoo

I recieved my proto board from BatchPCB.  Working fine.  No USB2 interface yet (waiting on parts).  Firmware needs some work now.

Oh and I'm using an ADS5424 14-bit @ 100 MHz now

board2i.jpg

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It looks really nice! Keep your eyes open for my post about a new board called the Benchy in the next couple hours. It integrates a FT232H USB chip with a Spartan6 and might make things easier for you.

Jack.

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Guest monkeydoo

Thanks.  Will look out for that.  You can tell PCB layout isn't my speciality.

Can you point me in the direction of the Papilio Plus UCF?

I'm doing some work porting my code to a Spartan6 target at the moment and could only turn up an old UCF for the Papilio Plus on hamsterworks.co.nz(?)

Cheers,

Ian

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I just checked in the latest version of the Papilio Plus EAGLE files and a generic ucf file over at GitHub:

https://github.com/GadgetFactory/Papilio-Plus

The ucf file can be downloaded directly from:

https://github.com/GadgetFactory/Papilio-Plus/raw/master/BPC3010-Papilio_Plus-general.ucf

The ucf file was generated using Kevin Lindsey's excellent pin converter tool which lets you generate ucf files for Papilio boards and Wings.

 

  Download the pin converter tool from:

  https://github.com/downloads/GadgetFactory/pin_converter/thelonious_pin_converter_latest.zip

 

  Or view his source code at:

  https://github.com/thelonious/pin_converter

 

  Jack.

 

 

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