Guest anirbax

Xilinx command line tools for bit gen and the static timing

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Guest anirbax

Hi guys,

I downloaded the Xilinx ISE Webpack, but realize that I don't need fancy GUI and 5GB download and multiples licences.

I have a lot of ASIC experience and I just need:

1) A Verilog synthesis tool to generate Spartan 3E .bit files, and some static timing checks

2) An HDL simulator, e.g., CVer

3) Papilio Programmer command line to download the bit file onto Papilio

4) The HDL, pin assignments and constraints I can write using my fav. text editor (gvim)

Now, I have (2, 3, 4) but (1) is what I don't know how to do on the command line using the ISE.

Does anyone know what are the command line tools for bit gen and the static timing that come with ISE?

Thanks,

Anirban

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Guest anirbax

Ok, I got the command line user guide from the Xilinx site and now going through the flow in detail.

Thanks for Papilio :-)

-Anirban

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Anirban,

Another tip that might be really helpful is to synthesize once using the standard Xilinx method. It generates a file called *.cmd_log. That file is a list of all the commands issued to build your project and can be renamed to *.cmd and run directly. :)

Jack.

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