Guest anirbax Posted October 19, 2011 Report Share Posted October 19, 2011 Hi guys, I downloaded the Xilinx ISE Webpack, but realize that I don't need fancy GUI and 5GB download and multiples licences. I have a lot of ASIC experience and I just need: 1) A Verilog synthesis tool to generate Spartan 3E .bit files, and some static timing checks 2) An HDL simulator, e.g., CVer 3) Papilio Programmer command line to download the bit file onto Papilio 4) The HDL, pin assignments and constraints I can write using my fav. text editor (gvim) Now, I have (2, 3, 4) but (1) is what I don't know how to do on the command line using the ISE. Does anyone know what are the command line tools for bit gen and the static timing that come with ISE? Thanks, Anirban Link to comment Share on other sites More sharing options...
Guest anirbax Posted October 19, 2011 Report Share Posted October 19, 2011 Ok, I got the command line user guide from the Xilinx site and now going through the flow in detail. Thanks for Papilio :-) -Anirban Link to comment Share on other sites More sharing options...
Jack Gassett Posted October 19, 2011 Report Share Posted October 19, 2011 Anirban, Another tip that might be really helpful is to synthesize once using the standard Xilinx method. It generates a file called *.cmd_log. That file is a list of all the commands issued to build your project and can be renamed to *.cmd and run directly. Jack. Link to comment Share on other sites More sharing options...
Guest anirbax Posted October 20, 2011 Report Share Posted October 20, 2011 Jack, thanks for the tip. I just compiled the stopwatch example that came with the Xilinx ISE download and downloaded the .bit file with Papilio Prog. Here is another resource that command line users might find useful: http://www.demandperipherals.com/docs/CmdLineFPGA.pdf Link to comment Share on other sites More sharing options...
alvieboy Posted October 20, 2011 Report Share Posted October 20, 2011 You can see how I do it by looking at Makefile, .xst, .ut and .prj files here: http://repo.or.cz/w/zpu/zpuino.git/tree/942cbb483bd12adf1abaeeafec52ea29b24d52b6:/zpu/hdl/zpuino/boards/papilio-one/s3e500 Link to comment Share on other sites More sharing options...
Jack Gassett Posted October 20, 2011 Report Share Posted October 20, 2011 Oh, And don't forget about Boldport, they have a Makefile generator. Jack. Link to comment Share on other sites More sharing options...
Recommended Posts
Archived
This topic is now archived and is closed to further replies.