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LCD Experiments

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Hi Alvaro,

The setup/hold times for data bursts are typically like 20ns each (-> 25MHz/2 pixel clock). The Zealot indeed went into emulation (loadb isn't implemented), so DWORD accesses speed it up. Might swap out the Zealot for the Zpuino core later...I assume you've cycle/pipeline optimized that?

Yes, byte and word addressing take as much as dword. However, due to IO registering they might take an extra cycle to complete.

I'm still a bit confused about the current ZPU development, the mailing list appears pretty dead. Are you the only one left working on the ZPU 'cutting edge' fronts?

Well, most people are more concerned with size than performance. I think I'm the only one trying to get both of two worlds, but it's rather complex thing.

Right now I'm focused on a 4-stage pipelined design, but might take a while to have it ready for production. Although numbers look good at this stage (at least for clock speed and clocks/instruction, let's see how it goes). It' still a bit large, and has some bugs.


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