Guest AtomSoft

COE Editor

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Guest AtomSoft

COE file is cool. Im not sure of its entire purpose but i made a COE viewer. The goal was to understand the file more and i think im getting it :D

What i plan to do next is create a COE editor for the VGA example. What this will allow is someone to create a basic screen for which you can draw over. like a background menu.

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Guest AtomSoft

Newer one now. Looks better. Now to make the simple line select and edit and live preview :)

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Alvaro is the guy who is behind the ZPUino soft processor and the VGA core that your coe tool is for.

He made Zetris, the ZPUino, and the VGA core.

Jack.

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Guest AtomSoft

Cool! I understand now :D i hope he like it then heh...  almost done coding the save portion.

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Guest AtomSoft

Here is newer video showing that saving works:

Converting new video that demonstrated it working right now.. then will upload it

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It looks like I have been causing some confusion here! I'm very sorry, I thought you were using the ZPUino VGA core, but it looks like you are actually using Kevin Lindsey's VGA core.

Saw your final video there, looks great. I was just talking to Kevin and it would be cool to turn this into a tool to make a simple menu interface that people can navigate with buttons.

Jack.

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Guest AtomSoft

Ok Cool, What about that external RAM board thats in development... ? Wouldnt it be possible to code a peripheral in VHDL to access it for VGA usage ?

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Not sure which of the boards (more than one exist) you're referring to.

I tried the C/RAM wing recently (the one with a CPLD +  SRAM) and found it very hard to work with at high speeds, due to Z->non-Z->Z latencies on CPLD. Still it might be useable at low speeds (ZPUino uses 96MHz as IO clock, that was too high for the CPLD, although data itself moved along very well).

However new boards are coming with integrated SRAM and I think I'll manage to boost a full VGA interface, full color, while still allowing RAM to be shared among VGA and CPU, and eventually other peripherals.

Stay tuned :)

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Guest AtomSoft

Cool! yah i was talking about C-Ram wing :)

On a side not... since im new to VHDL and all can  you explain how can i split a clock into 2 identical clocks ?

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I usually use a DCM's to derive clocks. I've been meaning to record a tutorial showing how to generate multiple clocks with different frequencies using a DCM.

Jack.

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Guest AtomSoft

Like that 32mhz internal clock, i want to use a dcm to change it to 9MHz, then i need to place that clock out to a pin but also need it for internal usage. Any thoughts

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Like that 32mhz internal clock, i want to use a dcm to change it to  9MHz, then i need to place that clock out to a pin but also need it for  internal usage. Any thoughts

Now, this depends if you require a perfect sync between clk/data on output/input pins, and whether if you need to sync between other clocks internally and also if you require a 50% duty cycle and 100% accuracy.

If I were you, I'd change 32MHz to something higher, but a multiple of 9MHz.

Like 36Mhz ( 32 * (9/8) ), or 72Mhz ( 32* (9/4) ).

Then I'd use regular flip flops to clock out the signal/data. If they are placed on IOB, then everything will be clocked out at same time. Using an enable signal will allow you to get the desired 9MHz, with 50% duty cycle.

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Guest AtomSoft

ah thanks a ton, i will give it a try. IOB is I/O Bank correct ? before i get lost :D

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IOB is I/O Bank correct ? before i get lost

Yes, it is. ISE/XST will place output FF's on IOB by default, but you can also instantiate OBUF/OBUFT if needed. Same for IBUF.

Álvaro

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Guest AtomSoft

Cool! im working on a better video for it soon. Like Creating entire screen or menus

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