alvieboy

Examples

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Since no one helped with a specific Papilio One demo, I only uploaded a S3ESK board demo, which uses LCD, rotary and leds.

http://alvie.loc/zpuino/examples.html

Ah, and Papilio One S3E500 bitfile is ready and available for download.

Jack: what do you think would be interesting demos/examples for Papilio ? Which wings would be more appropriate to this ?

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Hey Alvie,

I think the coolest demo that could be done for the Papilio One right now is something that uses the VGA Wing.

Other cool demos I've been thinking about:

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I think the coolest demo that could be done for the Papilio One right now is something that uses the VGA Wing.

I'm creating a simple VGA text interface (I don't have that much memory to use on the 250), let's see how it goes. I don't have a display at home, so I am not able to test it.

Stream MP3's over the USB port or from a SD card and output through the Audio Wing.

I can do this for WAV, not MP3. That would require HW implementation of at least IDCT. I might look at it later.

Make a frequency generator core that can be controlled with the ZPUino.

I just helped Shazz integrating a Yamaha YM2149 device in ZPUino, it seems to work now, if he finds no issues with it I will publish as an example.

Speech Synthesis - Eric Crabill put together a really awesome speech synthesis lab that I thought would be need to run on the Papilio. I think the phonemes file would have to be on the SPI Flash or SD card wing to work.

SPI is quite small, so a SD card would be better. You're thinking about streaming the phonemes using serial port ?

Álvaro

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SPI is quite small, so a SD card would be better. You're thinking about streaming the phonemes using serial port ?

Actually I was thinking about having Arduino code that would use the phonemes to say things. The phonemes would be sent out of an audio Wing. You could write Arduino sketches to say things.

I'm going to be at Maker Faire in San Francisco on the 21st and 22nd in the Seeed Studio both. They have been generous enough to offer space to present the Papilio One. So any demos we can present would be great.

So far I plan to show:

  • Pac-Man running on Papilio Arcade
  • Keyboard connected to Gateman Poly synthesizer
  • Arduino Sketches running on Papilio

I think speech synthesis would be an awesome demo too.

Jack.

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Looks like those phonemes are very small, and very low quality. I assume it uses the PICTalker phonemes.

Regarding VGA: do you have timings+pin information for your C/MEM wing ? That might allow a full VGA output, and I think ZPUino can handle the pace - that would allow some sort of demo, like the older 4K amazing PC demos of the nineties, with full resolution.

Álvaro

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The C/RAM Wing should work at speeds up to 100Mhz, although in practice I have not got that working yet. :)

All information for the C/RAM project is located at:

http://papilio.cc/index.php?n=Papilio.CRAMWing

I'll keep posting any new information there.

The source code, including the ucf file, for what I've done so far is on github.

https://github.com/GadgetFactory/C-RAM-Wing

ucf:https://github.com/GadgetFactory/C-RAM-Wing/blob/master/VHDL/CRAM_Wing_ISE/cram_wing.ucf

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After our conversation yesterday, and since I cannot test latest VGA I wrote, I moved on to a design for C/RAM that might be suitable for everyone use.

I actually wrote implementation and synthesized+fitted it, so to make sure we don't use more resources than those available on the CPLD.

So, my idea is like I told you to have a mix of SPI, wide-bus and bidirectional bus.

To accomplish that, the following signals are used to interface with CPU:

cpu_seln: Active 0 chip select, asynchronous.

cpu_we: CPU write enable, active high.

cpu_clk: CPU clock.

cpu_data: 13-bit data interface.

cpu_seln acts as an asynchronous reset signal for CPLD, and forces the bus to high-impedance.

A one-byte read cycle is performed by:

1) Selecting the device, by deasserting cpu_seln,

2) Presenting the lower 13-bit address in data interface,

3) let bus settle and rise the clock.

4) present the upper address bits in data interface, lower clock,

5) rise clock to clock in the full address,

6) CPU changes bus to high-impedance, lowers the clock

7) CPU rises the clock again,

8) CPLD presents 8-bits data on the data interface, cpu lowers clock,

9) CPU asserts cpu_seln

A multibyte read is similar, just repeat 7,8 and the address and low/high byte will be "incremented", so a full continuous read is possible.

Write is similar, just assert cpu_we when you're sending the upper address part. it will be latched.

I just need to test properly, I must avoid spurious writes to SRAM when clock is delayed/data changes.

What do you think ?

Álvaro

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Alvaro,

This sounds like an excellent scheme, once a C/RAM board arrives and I get back from Maker Faire lets dig deeper into this.

Jack.

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