Jack Gassett

Yet Another VGA Controller

Recommended Posts

I just created a new project over at GadgetForge for the "Yet Another VGA" controller core.

Original source page.

Gadget Forge Project Page.

I think this project is a great start for a standalone VHDL VGA core for the Papilio VGA Wing. Hopefully we can extend it to support things like graphic backgrounds and such. As it stands now it is more geared towards an Oscope type of display.

Head over to the project page for bitstreams that run on the Papilio One and the source  code that is ready to synthesize on the Papilio One.

Share this post


Link to post
Share on other sites
Guest pepevi

Very cool.

About the image that the example generates... is it animated or static? I see there are text capabilities but, how would you generate patterns or images?

Better than a tutorial, I think a video showing it off is needed  :D

Share this post


Link to post
Share on other sites

pepevi,

Well, it looks like if this core was placed under control of another core or a soft processor then the waveform and cursors could be updated realtime for animated display. As the core stands now it just shows a static waveform and cursors.

It is really meant as a base implementation for VGA, I'm hoping that someone is interested enough to extend it. What this really needs is some kind memory buffer that drives a graphics section. Or a way to put a bmp in SPI memory or something and then be able to add navigation options.

There is a cool looking VGA example from Xilinx for the Spartan 3A starter kit that does the above. I might implement that too but the problem with that is it is not Open Source.

Jack.

Share this post


Link to post
Share on other sites
Guest simmartin

Hi!

Jack already know that I'm very interested on this kind of project, for a device that I have to develop for work.

I had tried to load the papilio 250k bitstream inside my board, but it doesn't work... I have made myself the "VGA wing", with a connector and the resistors, but my monitor seems like to switch between a condition of signal present, to a condiction of signal absent with an interval of about 1 second ON/OFF.

I need some help to read the source code, and to understand exaclty where can I modify this code to implement a sort of "buffer" array of the monitor image... I'm absolutly not a fpga/vhdl expert (i'm more a newbie)...

My idea is to create a sort of buffer, where I can write the pixels color with a sort of microcontroller, like an external memory interface, or also the AVR Core inside the FPGA. I'm thinking of an external memory because with a resolution of 640x480 pixels and a 3 bit of color we need 921600 bit of information...but... I think I'm in wrong with something since the example should just store this information...

HEEEELP!!!!

Regards,

Simone

Share this post


Link to post
Share on other sites

Hello Simone,

The YAVGA is really more of a demo of what can be done.

Kevin Lindsey is doing a lot of good work on building a VGA core right now. He has a page up on the Papilio Playground.

I think the best bet is to band together and work together on it. He has a text mode working now and is working on adding sprites and such. The ultimate goal is to integrate it into the AVR8 soft processor. He has a lot of exciting ideas and is making some really nice progress. I think he will have something much better than the YAVGA very soon.

Kevin hangs out on the IRC channel and can be PM'd from the forum.

Jack.

Jack.

Share this post


Link to post
Share on other sites

Is there anyone interested in collaboration to develop a wing that contains ram and LCD interface instead of VGA? by LCD i mean bare LCD panels from repair laptop services. On eBay are quite cheap and range from small 7-10" to 17-19" and often all that they require is an inverter for backlight, a parallel or lvds interface hardware and data to be fed in with :) .

Of course in not all that easy but there are already some examples and moreover by often having digital parallel (or lvds) interfaces they don't require conversion to analog.

Pincount requirements might be an issue on papilio tough.

Share this post


Link to post
Share on other sites

You mean FPD (LVDS)?

I have not yet explored the possibility of having S3E output HDMI or DVI either. Do you know if our current FPGA can handle that bitstream rate at IOB level ?

Álvaro

Share this post


Link to post
Share on other sites

You mean FPD (LVDS)?

Yes but I some others display use plain TTL or LVTTL parallel interface i think.

I have not yet explored the possibility of having S3E output HDMI or DVI either. Do you know if our current FPGA can handle that bitstream rate at IOB level ?

Álvaro

I do not know what's the max bitstream rate on Spartan3E but I think it might depends on propagation time and maximum clock ratings.

I've found this document that tells "The maximum data rate for the Spartan-3E FPGA is

622 Mbps for the -4 speed grade and 666 Mbps for the -5 speed grade".

I hope that is the information you were looking for.

Share this post


Link to post
Share on other sites

If all goes well I hope to start a kickstarter project for the next generation Papilio board based on the Spartan 3A. The Spartan 3A has built in support to directly drive a DVI/HDMI monitor. Plus the new board will have SRAM built into, which will make this controller much, much easier to implement. :)

There is a Xilinx App note about implementing DVI/HDMI on the Spartan 3A.

http://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

This might be a good starting point. We could design a wing for the forthcoming board and be ready for it when the board is ready. :)

Jack.

Share this post


Link to post
Share on other sites

If all goes well I hope to start a kickstarter project for the next generation Papilio board based on the Spartan 3A. The Spartan 3A has built in support to directly drive a DVI/HDMI monitor. Plus the new board will have SRAM built into, which will make this controller much, much easier to implement. :)

how much ram? because we'll need plenty of it to implement a frame buffer at full color resolution! if my calculation are correct at least 1920x1080x24(bpp)x frame (minimum 2 to use the double buffering technique) =  99532800 bits or 99532800/(8*1024)=12150 or roughly 12 MB per frame.

There is a Xilinx App note about implementing DVI/HDMI on the Spartan 3A.

http://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

This might be a good starting point. We could design a wing for the forthcoming board and be ready for it when the board is ready. :)

Jack.

Thanks for the app. note it was very illuminating and if what is says it's correct I belive we could start to prototype the RAM wing even for this generation of papilio.

In fact we could try to drive lower res display and make the code scalable for higher res display by using registers to change height, width, ad color depth on the fly from the MCU / MPU or automatically by reading the n. of bits in the imput stream.

This will be good for testing the code on the current generation leaving the optimization of the pcb (read track impedance matching mainly) for the next papilio.

Share this post


Link to post
Share on other sites

The new board will support 4Mb, 8Mb, and 16Mb SRAM sizes.

Thanks for the info. I was asking myself  if it was possible to add  bigger ram or at least leave the possibility to add it after purchasing  the board (i.e leaving unpopulated pads).

What kind of Spartan3A package will the next papilio gen use? I'd like  to see a higher number of headers/pins (say twice the current to be sure  ). I'm asking because I wanted to try to develop a wing for the current papilio that contains DDR  DRAM and the chip to convert a 24bit RGB ttl datastream to LVDS which is  needed to for the LCD interface project. I think we need a  16 bit wide  data/ 24bit address bus (to address the minimum memory quantity  required),  Write enable, Read enable, Busy/Ready, Data/Address latch,  Data valid, and maybe other signals I forgot. Plus we need another bus  24bit wide and control signals for the lvds chip (i don't think we can  use the memory bus)

For the current papilio generation is possible to use a 32 bit wing  together with a 16 bit wing (or a 48bit wing)? On the website it says no  but there are 48 pin so it should be possible.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now