Jack Gassett

Papilio "Sump" Logic Analyzer

34 posts in this topic

The Papilio One can be used as a "Sump" Logic Analyzer just like the Open Bench Logic Sniffer.

The Project page is located here.

Download the latest binaries here.

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Hi

I was just wondering what the  difference  in the code is between the OLS version and the Papilio version.

Cheers

Nick

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Hello Nick,

The two share a common code base now, although I have not had the time to make the new "Sump" Verilog core work on the Papilio One yet, but I will soon.

The differences are:

  • The P1 has a 32Mhz external oscillator so a DCM is used to make the 100Mhz clock needed by the "Sump" core.
  • The P1 uses a UART core to communicate over the FT2232 chip while the OLS uses SPI to communicate with the PIC micro.
  • The OLS has voltage buffers built into one header which allows sampling 5V logic. The P1 has the option to add a Buffer Wing.

Jack.

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Hi Jack,

I recently built Papilio (500k) from the kit I bought from you. I tried to use it as a logic sniffer using various bit-files I downloaded from your site. I have some problems with it now.

Build 2.12 does not work for me at all - neither OLS client nor original SUMP client recognize Papilio at any speed I set. I got it from ZIP Papilio_One_Sump_LA_VHDL_source_2.12.zip.

Build, coming with Papilio Programmer PapilioOne_Logic_Analyzer_2.03_500k.bit works, I checked all 32 channels using improvised signal generator with Altera CPLD.

I found strange effect - when the OLS bitstream is loaded if you touch Xilinx, it becomes really hot really fast - may be capacitance to my finger matters at these frequencies. Open Logic Sniffer, though, does not behave this way. Can it keep it's oscillator down (I tried to sense the signal, Papilio always have 32MHz, OLD does not) while not working?

You mentioned that you're going to port new Verilog-based design to Papilio, and it's feature list is impressive. How is it going? I am a novice in FPGA, but if I can help somehow, I would gladly do what in my abilities. I only start learning FPGA/CPLD design now, my main specialty is programming.

Thank you for popularizing such an amazing technology.

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Hello victzh,

I haven't worked on porting the verilog core, but I have made a bunch of improvements to the source code for the VHDL core. I'm going to be out of the office most of the day today, but I'll put it on my list to release the new source code tomorrow.

Jack.

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Hi Jack,

did you manage to put out some new code for Papilio Logic Sniffer? If so, can you post the URL here.

Do you know why Papilio transmit captured data slower than OLS while both are running on 38400bit/s setting? And can I modify the firmware to set the rate faster?

I have another question regarding fast USB pipe to FPGA. I've seen in your playground a FT232H Wing, but did not find Eagle files for it. Do you share such files?

Also, you have a couple of errors in your Mouser BOM for FT232H Wing - the 12K resistor should be 1% - it's current reference, and EEPROM you use on board is SOT-23, while Mouser BOM has SOIC-8. Correct Mouser part is 579-93LC56BT-I/OT

Thanks, Victor

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Hello Victor,

I did check the much nicer and cleaner version of the VHDL Sump "Blaze" core into github. The latest tag that can be directly downloaded is here.

Do you know why Papilio transmit captured data slower than OLS while  both are running on 38400bit/s setting? And can I modify the firmware to  set the rate faster?

I've played around with increasing the speed with the "Blaze" core and have got it up to just under 1Mb/s but I can't get it to work reliably above that. I'm thinking that the Xilinx UART core may need to be integrated to get speeds up to 3Mb/s. There are comments in the top level file about how to adjust the speed, a lot of the work I did was with making the uart core more reliable and easier to understand.

I have another question regarding fast USB pipe to FPGA. I've seen  in your playground a FT232H Wing, but did not find Eagle files for it.  Do you share such files?

Well, we still hope to bring that design to market, until that happens it doesn't make sense to release the source files. Once we have the product being manufactured we will release the files. For now we have made the compromise of making the PCB available from BatchPCB for the people who want to try it out.

Thank you for the update on the BOM, I'll look at getting that updated.

Thanks!

Jack.

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Jack, I took a look at the Github repo, did not try it on my Papilio yet. You did not put already built image for 500k Spartan, didn't you? I can build it myself, I just wanted to make sure.

Also, what these mentions to SRAM in check-in comment refer to? Do you have a version with deep external memory? That would be very interesting.

What bit rate should I set in SUMP/OLS for this core?

Re FT232H files - pity, I wanted to modify this design a bit. First, I figured that for some reason your Wing footprint have holes a bit less than the headers I have when I made a two-directional buffer wing. Second, I don't like through hole crystal, I prefer SMD one (NX5032).

Thanks,

Victor.

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Victor,

I did the updates to the core in order to get it working with the new Spartan 6 boards that have 4Mb or SRAM available. Everything works good, but I haven't done any testing at higher speeds yet. Since my focus was more on testing with the new boards I did not generate any files for the 500K boards.

I think the default bit rate is 115200, there is a setting in the top level vhd file that you can modify to change the speed.

I'll PM you with the FT232H design, I'm just not ready to release it in the wild yet.

Jack.

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Jack, I built the image for 500K Papilio and uploaded it by Papilio loader. I checked port settings, as you directed, and they're set to 115200bit/s by default.

It does not work for me. Old image PapilioOne_Logic_Analyzer_2.03_500k.bit from Papilio Programmer bitstream_archive works OK, but only for 38400bit/s, so the FPGA is working.

OLS (I checked several versions, 0.9.4 and newer 0.95-b2) reports that device not found, while apparently successfully connecting to it.

The behavior when you connect terminal to Papilio is also different for two versions:

Old image does not output anything, apparently waiting for commands from the controlling program, the new one is spewing a stream of binary data immediately upon connection.

Can you tell me what I can do next to debug the thing?

Thanks,

Victor.

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Victor,

Are you using the Sump classic or Jawi's OLS client? Sump classic has a timeout that is too short and does not always work, give it a try with Jawi's OLS client.

Jack.

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Yes, I use Jawi's client, I even tried the most recent version of it.

The problem is somewhere else, not only the client, as far as I can tell. The behavior of new core on Papilio is too different from both the old core on Papilio and any core on OLS: new core starts transmitting a stream of binary data the very moment you open a connection to it. All other cores/platforms apparently wait for some instruction to do so from the host - at least they need to be instructed what parameters to use for data capture.

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Victor,

I just synth'ed the design for the Papilio One 500K and tested it with the Papilio One 500K board at 115200bps. Seems to work fine with Jawi's OLS client.

I checked the bit file into github, it can be downloaded here.

Hopefully that works for you and provides a frame of reference to get your own synthesis working.

Jack.

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Jack,

I made a set of interesting experiments with Papilio and OLS bitstream.

First of all, your bit file is no different from mine (with exception of string 16:09:10 in your file and 19:10:00 in mine, which can mean build time, as far as I can guess).

The results of loading these new bitfiles (I will call them Blaze) is intriguing. When you start capture with nothing connected to the board, it recognizes the device (and when you connect to it as a COM port, it is quiet), but the recorded signal (which should be constant at least) is very regular and reminds consequential stages of a counter.

When I connect a test source (CPLD with counter 16MHz down for 16 stages) it goes berserk and starts constantly spewing some binary data. Needless to say that OLS software fails to connect to the device in such state.

When I upload older 2.03 core it behaves normally - you can connect at 38400, record empty signal or actual counter - everything looks like it should be.

I am still not losing hope - it works properly with an older core, so I'll try to figure out what's going on with it further.

Thanks for building 500k bitstream for me, at least we excluded some causes.

Best,

Victor.

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Victor,

Hmmm, ok, I didn't do much testing beyond with capturing a signal on the build. I suspect what you are seeing could be related to the external trigger, we should look into how that is setup. With the OLS the trigger lines are much more isolated, with the Papilio the headers are right next to each other and can easily "bleed" over. We should put a pullup or pulldown resistor clause on the external trigger line in the ucf or disable it completely if it is the problem.

Jakc.

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I am planning to order PCBs for 5v buffer, do you think it make sense to have a two row footprint so that every signal on ribbon cable would coiside to ground, not unlike on IDE cables?

I mentioned that even on OLS there are some signal interference, visible if you use trigger on slow changing signals close to fast changing. Sometimes they overshoot to my slow signal.

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I'm considering getting the 500k, and would like to inquire about it's functionality first. I have the Logic Sniffer, which can't currently do continuous sampling. It's my understanding the problem with the logic sniffer is an issue in the PIC chip used on that device. So I wonder, when the logic analyzer is installed in this device, can it stream a continuous 1 terra byte file to SUMP for analysis? I don't really need a terra byte file, I just wanted to toss out a large number. It's OK if the max sample rate is 1MHz. 

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The max speed up the serial port is about 3Mbits/s, and at that speed most PCs have problems with input latency issues and/or the buffers getting swamped, causing data to be dropped. You sound as though you have a special design in mind? 

 

I've managed to get a Digilent Nexys2 board transferring at about 10MBytes/s (see http://hamsterworks.co.nz/mediawiki/index.php/Digilent_EPP_Performance), but you will need to use all the block RAM on the FPGA as a FIFO - if the PC has to pause for a 5ms for a disk I/O that requires 50KB of buffering on the FPGA!

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For the short term, I'm looking for just a logic analyzer option. For the longer term, I'm looking to use it embedded in an overall device, such that the overall system can have the logic analyzer on board. My long term goals and applications are open sources internal combustion engine control. 

 

Does the RLE help get better through put? I would like accurate time stamps of the crank angle which itself would happen on the order of 10k pulses per second. I don't know how many bits it takes to get the message down the USB, but it would seem at 10k pulses per second I have about 100 bits that can be used to transfer the data, which might be in the realm of possibility. Would RLE allow for a higher clock rate for better time stamp accuracy, but with a slower data stream?

 

Another quick question that I haven't been able to fully iron out. I think I can use this BPW5015 wing as a wing for the Papilio. This board specifies Papilio platform, and it appears to have the same pin out, but I ordered it as part of my Logic Sniffer aprox a year ago. I think I'm fine to use it as a buffer for the 500k, but I'm not 100% certain. Is this wing good for the 500k or do I need to obtain another wing?

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For the short term, I'm looking for just a logic analyzer option. For the longer term, I'm looking to use it embedded in an overall device, such that the overall system can have the logic analyzer on board. My long term goals and applications are open sources internal combustion engine control. 

My intention is to turn the OLS core into a wishbone core that can be used alongside with the ZPUino Soft Processor. This would fit in perfectly with what you are looking for.

 

Does the RLE help get better through put? I would like accurate time stamps of the crank angle which itself would happen on the order of 10k pulses per second. I don't know how many bits it takes to get the message down the USB, but it would seem at 10k pulses per second I have about 100 bits that can be used to transfer the data, which might be in the realm of possibility. Would RLE allow for a higher clock rate for better time stamp accuracy, but with a slower data stream?

If your data is repetitive or has large empty spaces then RLE will extend how long you can capture before running out of memory space.

 

Another quick question that I haven't been able to fully iron out. I think I can use this BPW5015 wing as a wing for the Papilio. This board specifies Papilio platform, and it appears to have the same pin out, but I ordered it as part of my Logic Sniffer aprox a year ago. I think I'm fine to use it as a buffer for the 500k, but I'm not 100% certain. Is this wing good for the 500k or do I need to obtain another wing?

Yes, it will work with the Papilio. It is input only though.

 

Jack.

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My intention is to turn the OLS core into a wishbone core that can be used alongside with the ZPUino Soft Processor. This would fit in perfectly with what you are looking for.

 

Yes that sounds exactly like what I would want. Can't wait to try it out. If there is anything I can do to help let me know. Alpha testing, Beta testing, or something like that. I'm not so good with VHDL yet, so probably not so good as a dev helper, but good as a power user.

 

If your data is repetitive or has large empty spaces then RLE will extend how long you can capture before running out of memory space.

 

Is that PC HDD memory, or FPGA device memory?

 

Yes, it will work with the Papilio. It is input only though.

Great that works for me. Thanks for the reply. 

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Yes that sounds exactly like what I would want. Can't wait to try it out. If there is anything I can do to help let me know. Alpha testing, Beta testing, or something like that. I'm not so good with VHDL yet, so probably not so good as a dev helper, but good as a power user.

 

 

Is that PC HDD memory, or FPGA device memory?

FPGA device memory, that is the biggest limiting factor right now.

 

Great that works for me. Thanks for the reply. 

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I am trying to get the Papilio One (500k) to work as a logic analyser using two level converter wings.

 

When I first got the Papilio One I spent some time installing software and playing with the device, and had as many problems as successes, so apologies if I am doing something really stupid.

 

I first tried to load the bit file from the webpage (http://papilio.cc/index.php?n=Papilio.SumpLogicAnalyzer) but it timed out. Not sure what the problem here is, but the link to github above worked a treat. Thank you.

 

When I plugged the board in Windows searched for drivers, and failed on 2 out of the 4 lines (sorry I didn't write down the messages).

 

I clicked on the bit file and the loader (v2.6 - is this now out of date?) came up. Now I wasn't sure whether I should write to the "FPGA" or "SPI Flash" or whether it doesn't matter. If I write to the "SPI Flash" do I need to unplug to allow the board to boot?

I tried FPGA first, but this led nowhere, so after plugging and unplugging of the USB and error messages in the log file of the loader, finally the board was seen as COM4 Papilio FPGA serial port. Lokking at properties it has picked up the Papilio driver (and not the FDTI driver???).

So I now programmed to "Flash" and this appeared to work, but the following mesages give me some doubt.

Programming External Flash Memory with "G:\uP\FPGA\Papilio\bit files\papilio_one_sump_blaze_p1_500k.bit".Found SST Flash (Pages=2048, Page Size=264 bytes, 4325376 bits).Erasing    :OkVerifying  :.....PassProgramming :..............Finished ProgrammingOkVerifying  :.....PassUsing devlist.txtDone.SPI execution time 7663.4 msUSB transactions: Write 2881 read 2164 retries 0JTAG chainpos: 0 Device IDCODE = 0x41c22093	Desc: XC3S500EUsing devlist.txtISC_Done       = 0ISC_Enabled    = 0House Cleaning = 1DONE           = 0

I then downloaded and fired up the Logic Sniffer from http://ols.lxtreme.nl/.

When I ran the shell script the tool appeared, and looks very smart indeed.

I wasn't sure what the firtst step was, but suspected that I needed to tell the tool about the board. I figured out that if I clicked on the down arrow, a window appeared where I could select serial port and device type. I chose COM4 (as seen in the device manager) and "Open Bench Logic Sniffer". When I clicked on "Show device metadata" the message "Detection failed!" appeared.

I can only guess that 1) the FPGA/SPI Flash has not been programmed 2) I have some settings in the tool incorrectly set.

BTW I did change the baud rate in the device manager to match the value in the tool, although again I'm not sure if this is really required for USB. BTW, do I need to select XON/XOFF by chance?a

 

FYI, I tried a different COMM package, and I do not see the LEDs near the FDTI flicker. Again I have no idea if this is diagnostic.

 

Any pointers and clarifications would be gratly appreciated.

 

I just tried plugging into another port.

USB Composite -> OK

USB Serial Converter A -> OK

USB Serial ConverterB -> OK

USB Serial Port (COM5) -> OK

USB Serial Port (COM6) -> OK

 

The COM ports are now FDTI and not Papilio.

 

In the tool I tried both COM5 and COM6 and then clicked "Show device metadata", but both failed.

 

regards...

 

--Gary
 

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