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Last night I ported some VGA type Verilog code from an Altera board to my Papilio One. I needed to generate a 65MHz internal clock, but was surprised at the lack of flexibility of the DCM_SP clock generator. I was able to relatively simply generate 64MHz, which was good enough and my old Dell VGA monitor synced correctly, however some of the clock phase controls needed to be tweaked. It occured to me that it might have been better to use a lower frequency reference crystal, such as 10MHz (or even lower if the DCM allows), as it would give more flexibility. I do of course realise that some frequencies will be impossible whatever the reference XTAL. Purely out of curiosity, I wondered why a frequency of 32MHz was selected? I also tried out adding a PLL to my blink Papilio Pro project, and found the same issue. 65MHz was not possible (only 64 or 66MHz). I checked the Altera project and the PLL was more flexible in that 65MHz was possible. I have seen some FPGA dev boards which use a programmable frequency chip, rather than a crystal and I can now see why that might be a really useful feature.