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The description (on 'papilio.cc') text for Papilio PRO "says": Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz. Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS). But I think that the USB schematic right below the text "says" the reverse. The JTAG-s go to ADBUS0..3, TXD abd RXD go to BDBUS0..1. And so says the published complete schematics for Papilio PRO. I am designing an own board based on ideas from the Papilio PRO schematics. I would rather really use Channel B for JTAG and channel A for data transfer. For then I can, with FT2232H as USB ctircuit, use synchronous FIFO245 for general data transfer. Only Channel A (FT2232H) supports synchronous FIFO245. How is the FPGA code uploaded into the flash? Is it all over the JTAG interface, or is it by implanting an application which reads data from the UART (RS) channel, writing them into the flash memory word by word? If the second is the truth, can Developement Studio handle the "reversed" USB addresses (COM ports, or...?)?