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Found 6 results

  1. Just purchased a Duo and LogicStart Shield and thought I'd get a heads up on the software/files needed. Trying to download the .ucf files for both and I'm getting a 404 error from hostgator. Dean
  2. I raised this question earlier but received no replies re: "Introducing the Spartan 3E FPGA and VHDL." Please tell me what is the difference is between the UCF notation with < > symbols vs. the notation with " " symbols? notation 1 is in book, but notation 2 is in some other sample code I received. Also, it appears that "IOSTANDARD=LVTTL" is not required. notation 1 from the book:NET LED_1 LOC = "Pxx" | IOSTANDARD=LVTTL;NET LED_0 LOC = "Pyy" | IOSTANDARD=LVTTL; notation 2:NET "LED<1>" LOC="Pxx" NET "LED<0>" LOC="Pyy"
  3. Version 1.1b

    1,240 downloads

    Generic UCF for Arcade MegaWing targeting the Papilio Pro and Papilio One.
  4. Version 1.2c

    3,366 downloads

    Generic UCF for the LogicStart MegaWing targeting the Papilio One
  5. (This includes observations and details that may be of use to other new users and those new to the Pro, as well as my own questions to follow.) What I'm using: Papilio Pro v1.3LogicStart MegaWing v1.2Windows 7Xilinx ISE Webpack 14.4 (Xilinx_ISE_DS_Win_14.4_P.49d.3.0 from the Vivado and ISE Design Suites download sub-section)Xilinx Device Pack 2012.4.1 (includes important updates for the WebPack)Papilio Loader-2.4-Setup-noJava (I already have Java)Notes: To the admin: There's a beta 2.0 Loader I stumbled across elsewhere on this site. It appears to be out-of-date.The loader may show an older version on its title bar. I've opened an issue with regard to this but it didn't cause problems for this example.Install the Papilio Loader, the Xilinx WebPack software, and the Xilinx Device Pack. Create the license for the free features of the ISE Design Suite and import that license (which you'll receive via email) to the ISE Design Suite. Open the ISE Design Suite and create a new HDL project with Spartan-6 settings appropriate to the Papilio Pro (Note that "Enable Message Filtering" is optional but useful): (At this point I'm mostly following the Intro to Spartan FPGA book with some important changes.) Add a new source VHDL module. Rather than using the wizard, I pasted in the source for this entity directly from the book (be sure to edit out any cruft if your copy spanned a page-break). Note that the entity name doesn't need to match the module name. Add an Implementation Constraints file (I called mine constraints.ucf). This was a little more tricky, since the pins in the book are for the Papilio One 500K, not the Pro. Retrieve the BPM7003-Papilio-Pro-LogicStart-MegaWing-general.ucf file and use it to find the appropriate pin mappings for the Pro (if you cut-and-paste these from the UCF, be sure to rename them accordingly!) This is what I used: NET SWITCH_0 LOC="P114" | IOSTANDARD=LVTTL; # C0NET SWITCH_1 LOC="P115" | IOSTANDARD=LVTTL; # C1NET LED_0 LOC="P123" | IOSTANDARD=LVTTL; # C8NET LED_1 LOC="P124" | IOSTANDARD=LVTTL; # C9Select the VHD file and you'll see the option in the pane below to "Generate Programming File". Run it. You shouldn't get any warnings or errors for this example. Plug in the Papilio Pro (with the LogicStart wing attached). Ensure the drivers load (it may take a short bit the first time you use it). Start the Loader and select the .bit file you just created in your project area (leave the .bmm and .hex file entries blank). Be sure "SPI Flash" is selected below "Write to". Select "Do Selected Operations" and wait for the programming process to complete successfully (there's troubleshooting info in the book and on the forums here). Try it out! The switches enabled by this module happen to control the LEDs above them. Change things! Swap switch_0 and switch_1 in the architecture section of the design, rebuild and upload again - now the switches control the opposite LEDs. Hopefully you find this quick-start useful! I have some questions which I'll add in the first comment below.
  6. Version 1.0

    302 downloads

    The Papilio Plus is a Papilo board with SRAM that is still in the prototyping phase. This is the generic ucf file for that board.