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Found 4 results

  1. Hi, I am new to the papilio enviro and to FPGA's ... (still expecting the 1st delivery) In good preparation of my plans with this device I studied alot opn the subject for a few weeks now and and read around in the existing forums. I started messing with VHDL in xilinx ISE .. The concept of FPGA's has attracted me much, but off course there is a lot to learn still .. I was wondering if it would be possible to used these wonderful 8 megs of SDRAM as video memory for VGA output .. ? If yes ... is it then possible to spilt it up and use the leftover as system RAM for some processor soft core (i was thinking of the 65816 because i have a past in that family) ? Or even better like putting it all in one flat address map where the soft core processor can manipulate the video memory direct random adressable ? I understand that access is limited by time slots .. but in burst modes you can do bulk transfers at high speeds .. but there must be alignment with read and write actions between the constant data refresh cycles ... I have seen the modules for testing the sdram .. but diving into that project in ISE is not a good start for beginners maybe since i did not really find a clear interface how to talk to the SDRAM controller module and translating it somehow into a flat always accesible way like the way you use SRAM.... Are there any experts who can elaborate a little more on this ? Grx.. Eric
  2. Hello, I'm also getting the "Cannot get programmer version, aborting" message when trying to upload a sketch to my Pro. I've tried the suggestions provided to others but continually get the same message. To date I've tried the following with no luck: - Ensuring that I have the correct port selected (tried again after removing every last trace of FTDI software from my Win7 pc). - Changing cables and ports on my pc. - The Zap 2.2.0 IDE bootloader approach as well as the approach described in the "LogicStart MegaWing Example" sketch. - Looking at it sternly to try and guilt it into working. - Ensured that Papillio Programmer is selected as the programmer. - Tried each of the Pro LX9 ZPUino boards when burning the bootloader and trying to upload code. I can see the TX light flashing when I try to upload and, as the others have stated, the AVR quickstart works just fine so I'm at a loss. My environment is Win7-64, Zap IDE 2.2.0, Loader 2.6 and the board says "BPC3011 V1.3". Any suggestions? Thanks, David
  3. rfunderburk

    Adding logic to ZPUino for Pro

    Hi - I have a need to add additional logic to the ZPUino-HDL project. To start I just try to compile the existing system and load it. This fails miserably. Here are my findings thus far: 1) The Makefile in the papilio-pro directory of the boards does not work with the 'standard' installation from Xilinx. It appears to rely on having mingw, or some other installation available. If I change the Makefile to use 'mkdir.exe' and 'rm.exe' then I am at least able to issue 'make' and 'make clean' (though 'clean' doesn't actually do anything due to differences in the specification of the file expansion). 2) The compilation completes, but the .map file does not match that in the repository (other than expected differences, like times, etc). There are some differences in the number of slices used and flip-flop counts. 3) Even though the compilation completes it will not execute when the .bit file is renamed and moved into the 'bitstreams' directory of the aruino-1.5. I believe that this is due to a bad .bmm file. I have tried to recreate a .bmm file, but there are many more BRAM16 (and one BRAM8) placements in the resultant output than are called out for in the .bmm file. So, how can I recompile the ZPUino-HDL to generate the .bit file for use in the arduino environment? Perhaps there are files that are not checked into the repository, as .gitignore is pretty extensive? Thanks, Richard
  4. MartyMacGyver

    Comparing the Papilio One with the Pro

    Beyond the various new features per the wiki page, how does the Papilio Pro stack up to the One (500K) in terms of its capacity to contain a given logic design, particularly the Arduino and ZPUino cores? My point of reference is this spec sheet. The One's XC3S500E appears to have far more slices compared to the Pro's XC6SLX9 (even when considering the 2:1(?) difference in slice sizes between the newer Spartan-6 and the older Spartan-3), but of course there's the new DSPs and such as well in the 6. Other than that, the Spartan-6 seems to have slightly fewer logic cells and slightly more flip-flops (but do those numbers include what's in the slices, etc.?) Thanks in advance, and if this is all covered elsewhere already just let me know... so far I haven't stumbled upon a head-to-head comparison of the Pro vs the One 500K with these details, and that'd be useful info for people switching to the Pro (or, like me, starting out with it).