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Found 1 result

  1. ISE Placement Error

    Hi, I am trying out the newbie example here: (plan to load design onto a Papilio One 250) Running synthesis gives this error: Starting Placer Phase 1.1 ERROR:Place:311 - The IOB clk is locked to site IPAD21 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. The constraint file (downloaded from here) NET clk LOC="P89" | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns; When I change the IO type to IOSTANDARD=LVCMOS33, PnR completes without error. What could be the reason why 2.5V CMOS is not supported? Thanks Anirban