Search the Community
Showing results for tags 'oddr2'.
Found 1 result
My second newbie question, hopefully someone can help me and I'll be forever grateful. I'm using my recently purchased Papilio one 500k to create a 24MHz clock output to feed into a different chip/module. Why am I doing this? Because I bought the wrong oscillator for my other module and I thought hooking it up on the fpga would a quick temp solution. The design is super simple, just the regular 32Mhz clk in, to a DCM which modulate to 24Mhz, then to ODDR2 which drives an OBUF on one of the IO pins. The output pin is set as LVCMOS33 in my ucf and the OBUF driving it is also LVCMOS33 standard. However, when I measure the output on the board with an oscilloscope, the waveforms are really distorted but correct frequency. As if there's too much parasitic cap on the output. Going down to a much smaller freq around 8Mhz the waveforms are much more square. I've calibrated my probes over and over again. Are the "wings" or headers on the Papilio bad for driving such signal? Or do I need to change some iostandard or drive strength? Any advice suggestion? Thanks