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  1. Hello, I'm a rank newbie to FPGAs and the various design languages. I've been studying the J1 forth core and pretty much understand most of the Verilog code. The following construct however has puzzled. I understand that dsp is the data stack pointer and that it is 5 bits wide for the 32 words making up the data stack reg [4:0] dsp; // Data stack pointer Here I understand the data stack offset is extracted from the instruction as a 2 bit value wire [1:0] dd = insn[1:0]; // D stack delta This expression is what I don't understand _dsp = dsp + {dd[1], dd[1], dd[1], dd}; Can anyone enlighten me about what this is doing? Thanks in advance