Search the Community: Showing results for tags 'flash'.
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Andrew Baldwin posted a topic in Papilio DUOHello Forum, My first time on a Forum, hope I get the etiquette correct. Recently got my Papilio Duo and a LogicStart wingy, itching to get it all running. Intend to VHDL, not drag and drop...that's the intention anyway. Essentially, being from an electronics background, I like to know what's going on. To that end, I've been wading my way through the plethora of Xilinx datasheets associated with the Spartan-6-LX9. At the moment I have couple of quick questions for the collective forumers The LX9 FPGA is set with M0 =1 and M1 =0, this sets the device in Serial Master Mode so it will get its configuration bit stream from the Flash on power up or if PROGRAM_B is pulled low, so : 1) How does data from the PC get programmed to the Flash? 2) I see other questions relating to the PC software configuring the FPGA directly through the USB port,, am I missing something in the circuit diagram, I cant see how this is possible? Unless there is something pre-configured, pre-programmed that we are shielded from....... hope they're not too stupid questions. Thanks Andrew
anirbax posted a topic in Papilio OneHi, Is it possible to access the SPI flash on the Papillio One board from my Verilog code? Some part of the flash is taken by the bitfile for loading FPGA configuration, and I'd like to use some free flash blocks (a few hundred bytes) My RTL receives data from a UART interface, processes it (SHA-1) and needs to store the signature on non-volatile storage. If not, I will have to get a separate SPI flash chip for storage. Thanks Anirban
Hi, I know that in general the configuration memory of FPGAs can be accessed and used with some limitations. And as the ZPUino loads it's program from the FLASH I would be very interested to know if it's possible to store and read some values from the sketch? Thanks, Tobias
I'm trying to build the ./bscan_spi_xc6slx9.bit file from source, to program the flash on my Papilio Pro board. From the git source, the only .v or .vhdl source file for Spartan 6 is: ./xc3sprog/trunk/bscan_spi/bscan_s6_spi_isf_ext.v Is this the one I should use? Then for the User Constraints File, the only relevant one I can find is the generic one, The two files obviously don't match, so I from the .ucf file I removed everything except the FLASH_* lines. And in the .v file, I replaced all the MOSI/MISO lines with the FLASH_SI/SO etc lines, like: module top ( output wire FLASH_SI, //MOSI, output wire FLASH_CS, //CSB, output wire FLASH_CK, //DRCK1, input FLASH_SO //MISO ); (and all other places) The resulting .v & .ucf files do generate a bscan .bit file, but when I use that to program the flash, I get this: ./papilio-prog -f ../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit -b ~joostje/VHDL/bscan-Papilio/top.bit -v Using built-in device list JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "/home/joostje/VHDL/bscan-Papilio/top.bit". DNA is 0xb9c95021930a5ffe Done. Programming time 547.0 ms Programming External Flash Memory with "../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit". Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. USB transactions: Write 178 read 10 retries 8 Using the original bscan_spi_xc6slx9.bit does work: As for the reason why I want to build the source (apart from "I should be able to"), I'm using a modified Papilio board design with a Spartan XC6SLX16 (256 pin BGA), So I need to generate a new bitfile for that XC6SLX16. So, doesn anyone know where the .v or .vhdl source files (preferably with a .ucf file) are that can generate a .bit file for the Spartan 6 (Papilio Pro)? Papilio-Loader source was this morning cloned from here: https://github.com/GadgetFactory/Papilio-Loader.git (I've attached my modified .ucf and .v files, both renamed to .txt as the uploader didn't like my .ucf extention) Thanks, joost BPC3011-Papilio_Pro-general.txt bscan_s6_spi_isf_ext.txt