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HELLO all, just started my papilio journey and I need to reduce the 32MHz internal clock down to just 5Hz. I tried reading materials about the CMT (clock management tile) but just got more confused. thank u Mar

Hi, I may have not dug enough into the Papilo FPGA cards documentation yet, so I am asking here: What about removing the clock? to work in asynchronous mode. How difficult is this with the different cards (I am yet considering buying the Papilio Pro, but answers for the other cards are also welcomed). Does anyone already did it? For information, I am trying to reproduce some results of Dr. David Rosin from Duke University / Technische üniversität Berlin (http://fds.duke.edu/db/aas/Physics/researchers/dpr12), so I really need this asynchronous mode. And I would not go for proprietary devices Best, Julien

My second newbie question, hopefully someone can help me and I'll be forever grateful. I'm using my recently purchased Papilio one 500k to create a 24MHz clock output to feed into a different chip/module. Why am I doing this? Because I bought the wrong oscillator for my other module and I thought hooking it up on the fpga would a quick temp solution. The design is super simple, just the regular 32Mhz clk in, to a DCM which modulate to 24Mhz, then to ODDR2 which drives an OBUF on one of the IO pins. The output pin is set as LVCMOS33 in my ucf and the OBUF driving it is also LVCMOS33 standard. However, when I measure the output on the board with an oscilloscope, the waveforms are really distorted but correct frequency. As if there's too much parasitic cap on the output. Going down to a much smaller freq around 8Mhz the waveforms are much more square. I've calibrated my probes over and over again. Are the "wings" or headers on the Papilio bad for driving such signal? Or do I need to change some iostandard or drive strength? Any advice suggestion? Thanks